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Commit ef3adc18 authored by Philipp Zabel's avatar Philipp Zabel Committed by Shawn Guo
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ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr 



Masks for IPU AXI transaction QoS settings

Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 8d9ee21e

include/linux/mfd/syscon/imx6q-iomuxc-gpr.h

+18 −0
Original line number Original line Diff line number Diff line
@@ -242,6 +242,24 @@ 




#define IMX6Q_GPR5_L2_CLK_STOP			BIT(8)

#define IMX6Q_GPR5_L2_CLK_STOP			BIT(8)





#define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK	(0xf << 0)

#define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK	(0xf << 4)

#define IMX6Q_GPR6_IPU1_ID10_WR_QOS_MASK	(0xf << 8)

#define IMX6Q_GPR6_IPU1_ID11_WR_QOS_MASK	(0xf << 12)

#define IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK	(0xf << 16)

#define IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK	(0xf << 20)

#define IMX6Q_GPR6_IPU1_ID10_RD_QOS_MASK	(0xf << 24)

#define IMX6Q_GPR6_IPU1_ID11_RD_QOS_MASK	(0xf << 28)



#define IMX6Q_GPR7_IPU2_ID00_WR_QOS_MASK	(0xf << 0)

#define IMX6Q_GPR7_IPU2_ID01_WR_QOS_MASK	(0xf << 4)

#define IMX6Q_GPR7_IPU2_ID10_WR_QOS_MASK	(0xf << 8)

#define IMX6Q_GPR7_IPU2_ID11_WR_QOS_MASK	(0xf << 12)

#define IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK	(0xf << 16)

#define IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK	(0xf << 20)

#define IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK	(0xf << 24)

#define IMX6Q_GPR7_IPU2_ID11_RD_QOS_MASK	(0xf << 28)



#define IMX6Q_GPR8_TX_SWING_LOW			(0x7f << 25)

#define IMX6Q_GPR8_TX_SWING_LOW			(0x7f << 25)

#define IMX6Q_GPR8_TX_SWING_FULL		(0x7f << 18)

#define IMX6Q_GPR8_TX_SWING_FULL		(0x7f << 18)

#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB		(0x3f << 12)

#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB		(0x3f << 12)