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Commit ef1d9fee authored by Xing Zheng's avatar Xing Zheng Committed by Heiko Stuebner
Browse files

clk: rockchip: Add support for multiple clock providers 



There are need to support Multi-CRUs probability in future, but
it is not supported on the current Rockchip Clock Framework.

Therefore, this patch add support a provider as the parameter
handler when we call the clock register functions for per CRU.

Signed-off-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 268aebaa

drivers/clk/rockchip/clk-pll.c

+17 −13
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ struct rockchip_clk_pll { 
	const struct rockchip_pll_rate_table *rate_table;

	unsigned int		rate_count;

	spinlock_t		*lock;



	struct rockchip_clk_provider *ctx;

};



#define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
@@ -90,7 +92,7 @@ static long rockchip_pll_round_rate(struct clk_hw *hw, 
 */

static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)

{

	struct regmap *grf = rockchip_clk_get_grf();

	struct regmap *grf = rockchip_clk_get_grf(pll->ctx);

	unsigned int val;

	int delay = 24000000, ret;
@@ -251,7 +253,7 @@ static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, 
	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);

	const struct rockchip_pll_rate_table *rate;

	unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate);

	struct regmap *grf = rockchip_clk_get_grf();

	struct regmap *grf = rockchip_clk_get_grf(pll->ctx);



	if (IS_ERR(grf)) {

		pr_debug("%s: grf regmap not available, aborting rate change\n",
@@ -490,7 +492,7 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, 
	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);

	const struct rockchip_pll_rate_table *rate;

	unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);

	struct regmap *grf = rockchip_clk_get_grf();

	struct regmap *grf = rockchip_clk_get_grf(pll->ctx);



	if (IS_ERR(grf)) {

		pr_debug("%s: grf regmap not available, aborting rate change\n",
@@ -563,7 +565,7 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) 
		 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);

	if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf

						     || rate->nb != cur.nb) {

		struct regmap *grf = rockchip_clk_get_grf();

		struct regmap *grf = rockchip_clk_get_grf(pll->ctx);



		if (IS_ERR(grf))

			return;
@@ -595,12 +597,13 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = { 
 * Common registering of pll clocks

 */



struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,

struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,

		enum rockchip_pll_type pll_type,

		const char *name, const char *const *parent_names,

		u8 num_parents, void __iomem *base, int con_offset,

		int grf_lock_offset, int lock_shift, int mode_offset,

		int mode_shift, struct rockchip_pll_rate_table *rate_table,

		u8 clk_pll_flags, spinlock_t *lock)

		u8 num_parents, int con_offset, int grf_lock_offset,

		int lock_shift, int mode_offset, int mode_shift,

		struct rockchip_pll_rate_table *rate_table,

		u8 clk_pll_flags)

{

	const char *pll_parents[3];

	struct clk_init_data init;
@@ -624,11 +627,11 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, 
	/* create the mux on top of the real pll */

	pll->pll_mux_ops = &clk_mux_ops;

	pll_mux = &pll->pll_mux;

	pll_mux->reg = base + mode_offset;

	pll_mux->reg = ctx->reg_base + mode_offset;

	pll_mux->shift = mode_shift;

	pll_mux->mask = PLL_MODE_MASK;

	pll_mux->flags = 0;

	pll_mux->lock = lock;

	pll_mux->lock = &ctx->lock;

	pll_mux->hw.init = &init;



	if (pll_type == pll_rk3036 || pll_type == pll_rk3066)
@@ -695,11 +698,12 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, 


	pll->hw.init = &init;

	pll->type = pll_type;

	pll->reg_base = base + con_offset;

	pll->reg_base = ctx->reg_base + con_offset;

	pll->lock_offset = grf_lock_offset;

	pll->lock_shift = lock_shift;

	pll->flags = clk_pll_flags;

	pll->lock = lock;

	pll->lock = &ctx->lock;

	pll->ctx = ctx;



	pll_clk = clk_register(NULL, &pll->hw);

	if (IS_ERR(pll_clk)) {

drivers/clk/rockchip/clk-rk3036.c

+12 −5
Original line number Diff line number Diff line
@@ -440,6 +440,7 @@ static const char *const rk3036_critical_clocks[] __initconst = { 


static void __init rk3036_clk_init(struct device_node *np)

{

	struct rockchip_clk_provider *ctx;

	void __iomem *reg_base;

	struct clk *clk;
@@ -449,22 +450,26 @@ static void __init rk3036_clk_init(struct device_node *np) 
		return;

	}



	rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	if (IS_ERR(ctx)) {

		pr_err("%s: rockchip clk init failed\n", __func__);

		return;

	}



	clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock usb480m: %ld\n",

			__func__, PTR_ERR(clk));



	rockchip_clk_register_plls(rk3036_pll_clks,

	rockchip_clk_register_plls(ctx, rk3036_pll_clks,

				   ARRAY_SIZE(rk3036_pll_clks),

				   RK3036_GRF_SOC_STATUS0);

	rockchip_clk_register_branches(rk3036_clk_branches,

	rockchip_clk_register_branches(ctx, rk3036_clk_branches,

				  ARRAY_SIZE(rk3036_clk_branches));

	rockchip_clk_protect_critical(rk3036_critical_clocks,

				      ARRAY_SIZE(rk3036_critical_clocks));



	rockchip_clk_register_armclk(ARMCLK, "armclk",

	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",

			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),

			&rk3036_cpuclk_data, rk3036_cpuclk_rates,

			ARRAY_SIZE(rk3036_cpuclk_rates));
@@ -472,6 +477,8 @@ static void __init rk3036_clk_init(struct device_node *np) 
	rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),

				  ROCKCHIP_SOFTRST_HIWORD_MASK);



	rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);

	rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);



	rockchip_clk_of_add_provider(np, ctx);

}

CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);

drivers/clk/rockchip/clk-rk3188.c

+31 −13
Original line number Diff line number Diff line
@@ -759,57 +759,74 @@ static const char *const rk3188_critical_clocks[] __initconst = { 
	"hclk_cpubus"

};



static void __init rk3188_common_clk_init(struct device_node *np)

static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)

{

	struct rockchip_clk_provider *ctx;

	void __iomem *reg_base;



	reg_base = of_iomap(np, 0);

	if (!reg_base) {

		pr_err("%s: could not map cru region\n", __func__);

		return;

		return ERR_PTR(-ENOMEM);

	}



	rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	if (IS_ERR(ctx)) {

		pr_err("%s: rockchip clk init failed\n", __func__);

		return ERR_PTR(-ENOMEM);

	}



	rockchip_clk_register_branches(common_clk_branches,

	rockchip_clk_register_branches(ctx, common_clk_branches,

				  ARRAY_SIZE(common_clk_branches));



	rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),

				  ROCKCHIP_SOFTRST_HIWORD_MASK);



	rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);

	rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);



	return ctx;

}



static void __init rk3066a_clk_init(struct device_node *np)

{

	rk3188_common_clk_init(np);

	rockchip_clk_register_plls(rk3066_pll_clks,

	struct rockchip_clk_provider *ctx;



	ctx = rk3188_common_clk_init(np);

	if (IS_ERR(ctx))

		return;



	rockchip_clk_register_plls(ctx, rk3066_pll_clks,

				   ARRAY_SIZE(rk3066_pll_clks),

				   RK3066_GRF_SOC_STATUS);

	rockchip_clk_register_branches(rk3066a_clk_branches,

	rockchip_clk_register_branches(ctx, rk3066a_clk_branches,

				  ARRAY_SIZE(rk3066a_clk_branches));

	rockchip_clk_register_armclk(ARMCLK, "armclk",

	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",

			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),

			&rk3066_cpuclk_data, rk3066_cpuclk_rates,

			ARRAY_SIZE(rk3066_cpuclk_rates));

	rockchip_clk_protect_critical(rk3188_critical_clocks,

				      ARRAY_SIZE(rk3188_critical_clocks));

	rockchip_clk_of_add_provider(np, ctx);

}

CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);



static void __init rk3188a_clk_init(struct device_node *np)

{

	struct rockchip_clk_provider *ctx;

	struct clk *clk1, *clk2;

	unsigned long rate;

	int ret;



	rk3188_common_clk_init(np);

	rockchip_clk_register_plls(rk3188_pll_clks,

	ctx = rk3188_common_clk_init(np);

	if (IS_ERR(ctx))

		return;



	rockchip_clk_register_plls(ctx, rk3188_pll_clks,

				   ARRAY_SIZE(rk3188_pll_clks),

				   RK3188_GRF_SOC_STATUS);

	rockchip_clk_register_branches(rk3188_clk_branches,

	rockchip_clk_register_branches(ctx, rk3188_clk_branches,

				  ARRAY_SIZE(rk3188_clk_branches));

	rockchip_clk_register_armclk(ARMCLK, "armclk",

	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",

				  mux_armclk_p, ARRAY_SIZE(mux_armclk_p),

				  &rk3188_cpuclk_data, rk3188_cpuclk_rates,

				  ARRAY_SIZE(rk3188_cpuclk_rates));
@@ -833,6 +850,7 @@ static void __init rk3188a_clk_init(struct device_node *np) 


	rockchip_clk_protect_critical(rk3188_critical_clocks,

				      ARRAY_SIZE(rk3188_critical_clocks));

	rockchip_clk_of_add_provider(np, ctx);

}

CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);

drivers/clk/rockchip/clk-rk3228.c

+12 −5
Original line number Diff line number Diff line
@@ -628,6 +628,7 @@ static const char *const rk3228_critical_clocks[] __initconst = { 


static void __init rk3228_clk_init(struct device_node *np)

{

	struct rockchip_clk_provider *ctx;

	void __iomem *reg_base;



	reg_base = of_iomap(np, 0);
@@ -636,17 +637,21 @@ static void __init rk3228_clk_init(struct device_node *np) 
		return;

	}



	rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	if (IS_ERR(ctx)) {

		pr_err("%s: rockchip clk init failed\n", __func__);

		return;

	}



	rockchip_clk_register_plls(rk3228_pll_clks,

	rockchip_clk_register_plls(ctx, rk3228_pll_clks,

				   ARRAY_SIZE(rk3228_pll_clks),

				   RK3228_GRF_SOC_STATUS0);

	rockchip_clk_register_branches(rk3228_clk_branches,

	rockchip_clk_register_branches(ctx, rk3228_clk_branches,

				  ARRAY_SIZE(rk3228_clk_branches));

	rockchip_clk_protect_critical(rk3228_critical_clocks,

				      ARRAY_SIZE(rk3228_critical_clocks));



	rockchip_clk_register_armclk(ARMCLK, "armclk",

	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",

			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),

			&rk3228_cpuclk_data, rk3228_cpuclk_rates,

			ARRAY_SIZE(rk3228_cpuclk_rates));
@@ -654,6 +659,8 @@ static void __init rk3228_clk_init(struct device_node *np) 
	rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),

				  ROCKCHIP_SOFTRST_HIWORD_MASK);



	rockchip_register_restart_notifier(RK3228_GLB_SRST_FST, NULL);

	rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL);



	rockchip_clk_of_add_provider(np, ctx);

}

CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);

drivers/clk/rockchip/clk-rk3288.c

+13 −6
Original line number Diff line number Diff line
@@ -881,6 +881,7 @@ static struct syscore_ops rk3288_clk_syscore_ops = { 


static void __init rk3288_clk_init(struct device_node *np)

{

	struct rockchip_clk_provider *ctx;

	struct clk *clk;



	rk3288_cru_base = of_iomap(np, 0);
@@ -889,7 +890,11 @@ static void __init rk3288_clk_init(struct device_node *np) 
		return;

	}



	rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);

	ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);

	if (IS_ERR(ctx)) {

		pr_err("%s: rockchip clk init failed\n", __func__);

		return;

	}



	/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */

	clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
@@ -897,17 +902,17 @@ static void __init rk3288_clk_init(struct device_node *np) 
		pr_warn("%s: could not register clock pclk_wdt: %ld\n",

			__func__, PTR_ERR(clk));

	else

		rockchip_clk_add_lookup(clk, PCLK_WDT);

		rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);



	rockchip_clk_register_plls(rk3288_pll_clks,

	rockchip_clk_register_plls(ctx, rk3288_pll_clks,

				   ARRAY_SIZE(rk3288_pll_clks),

				   RK3288_GRF_SOC_STATUS1);

	rockchip_clk_register_branches(rk3288_clk_branches,

	rockchip_clk_register_branches(ctx, rk3288_clk_branches,

				  ARRAY_SIZE(rk3288_clk_branches));

	rockchip_clk_protect_critical(rk3288_critical_clocks,

				      ARRAY_SIZE(rk3288_critical_clocks));



	rockchip_clk_register_armclk(ARMCLK, "armclk",

	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",

			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),

			&rk3288_cpuclk_data, rk3288_cpuclk_rates,

			ARRAY_SIZE(rk3288_cpuclk_rates));
@@ -916,8 +921,10 @@ static void __init rk3288_clk_init(struct device_node *np) 
				  rk3288_cru_base + RK3288_SOFTRST_CON(0),

				  ROCKCHIP_SOFTRST_HIWORD_MASK);



	rockchip_register_restart_notifier(RK3288_GLB_SRST_FST,

	rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST,

					   rk3288_clk_shutdown);

	register_syscore_ops(&rk3288_clk_syscore_ops);



	rockchip_clk_of_add_provider(np, ctx);

}

CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);