Merge "clk: qcom: clk-alpha-pll: Add support for is_enabled ops" (eefb00cc) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/clk/qcom/clk-alpha-pll.c

+30 −2

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
		* Copyright (c) 2015-2017, 2020, The Linux Foundation. All rights reserved.
		*
		* This software is licensed under the terms of the GNU General Public
		* License version 2, as published by the Free Software Foundation, and
		@@ -554,12 +554,30 @@ void clk_fabia_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		pll->inited = true;
		}

		static int clk_fabia_pll_enable(struct clk_hw *hw)
		static int pll_is_enabled(struct clk_hw *hw, u32 mask)
		{
		int ret;
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		u32 val, off = pll->offset;

		ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
		if (ret)
		return ret;

		return !!(val & mask);
		}

		static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
		{
		return pll_is_enabled(hw, PLL_LOCK_DET);
		}

		static int clk_fabia_pll_enable(struct clk_hw *hw)
		{
		int ret;
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		u32 val, opmode_val, off = pll->offset;

		ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
		if (ret)
		return ret;
		@@ -572,6 +590,14 @@ static int clk_fabia_pll_enable(struct clk_hw *hw)
		return wait_for_pll_enable(pll, PLL_ACTIVE_FLAG);
		}

		ret = regmap_read(pll->clkr.regmap, off + FABIA_OPMODE, &opmode_val);
		if (ret)
		return ret;

		/* Skip If PLL is already running */
		if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
		return 0;

		if (unlikely(!pll->inited))
		clk_fabia_pll_configure(pll, pll->clkr.regmap, pll->config);

		@@ -751,6 +777,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
		const struct clk_ops clk_fabia_pll_ops = {
		.enable = clk_fabia_pll_enable,
		.disable = clk_fabia_pll_disable,
		.is_enabled = clk_alpha_pll_is_enabled,
		.recalc_rate = clk_fabia_pll_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		.set_rate = clk_fabia_pll_set_rate,
		@@ -761,6 +788,7 @@ EXPORT_SYMBOL_GPL(clk_fabia_pll_ops);
		const struct clk_ops clk_fabia_fixed_pll_ops = {
		.enable = clk_fabia_pll_enable,
		.disable = clk_fabia_pll_disable,
		.is_enabled = clk_alpha_pll_is_enabled,
		.recalc_rate = clk_fabia_pll_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		.list_registers = clk_fabia_pll_list_registers,

drivers/clk/qcom/clk-rcg2.c

+14 −2

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2013, 2016-2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2013, 2016-2018, 2020,
		*
		* The Linux Foundation. All rights reserved.
		*
		* This software is licensed under the terms of the GNU General Public
		* License version 2, as published by the Free Software Foundation, and
		@@ -248,6 +250,7 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
		const struct freq_tbl *f_curr;
		u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
		unsigned long recalc_rate;

		if (rcg->flags & DFS_ENABLE_RCG)
		return rcg->current_freq;
		@@ -285,7 +288,16 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
		hid_div &= mask;
		}

		return clk_rcg2_calc_rate(parent_rate, m, n, mode, hid_div);
		recalc_rate = clk_rcg2_calc_rate(parent_rate, m, n, mode, hid_div);

		/*
		* Check the case when the RCG has been initialized to a non-CXO
		* frequency.
		*/
		if (rcg->enable_safe_config && !rcg->current_freq)
		rcg->current_freq = recalc_rate;

		return recalc_rate;
		}

		static int _freq_tbl_determine_rate(struct clk_hw *hw,