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Commit eee64b70 authored by Sascha Hauer's avatar Sascha Hauer Committed by Boris Brezillon
Browse files

mtd: nand: Introduce nand_data_interface 



Currently we have no data structure to fully describe a NAND timing.
We only have struct nand_sdr_timings for NAND timings in SDR mode,
but nothing for DDR mode and also no container to store both types
of timing.
This patch adds struct nand_data_interface which stores the timing
type and a union of different timings. This can be used to pass to
drivers in order to configure the timing.
Add kerneldoc for struct nand_sdr_timings while touching it anyway.

Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
parent 2f94abfe

include/linux/mtd/nand.h

+117 −49
Original line number Diff line number Diff line
@@ -572,6 +572,123 @@ struct nand_buffers { 
	uint8_t *databuf;

};



/**

 * struct nand_sdr_timings - SDR NAND chip timings

 *

 * This struct defines the timing requirements of a SDR NAND chip.

 * These information can be found in every NAND datasheets and the timings

 * meaning are described in the ONFI specifications:

 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing

 * Parameters)

 *

 * All these timings are expressed in picoseconds.

 *

 * @tALH_min: ALE hold time

 * @tADL_min: ALE to data loading time

 * @tALS_min: ALE setup time

 * @tAR_min: ALE to RE# delay

 * @tCEA_max: CE# access time

 * @tCEH_min:

 * @tCH_min:  CE# hold time

 * @tCHZ_max: CE# high to output hi-Z

 * @tCLH_min: CLE hold time

 * @tCLR_min: CLE to RE# delay

 * @tCLS_min: CLE setup time

 * @tCOH_min: CE# high to output hold

 * @tCS_min: CE# setup time

 * @tDH_min: Data hold time

 * @tDS_min: Data setup time

 * @tFEAT_max: Busy time for Set Features and Get Features

 * @tIR_min: Output hi-Z to RE# low

 * @tITC_max: Interface and Timing Mode Change time

 * @tRC_min: RE# cycle time

 * @tREA_max: RE# access time

 * @tREH_min: RE# high hold time

 * @tRHOH_min: RE# high to output hold

 * @tRHW_min: RE# high to WE# low

 * @tRHZ_max: RE# high to output hi-Z

 * @tRLOH_min: RE# low to output hold

 * @tRP_min: RE# pulse width

 * @tRR_min: Ready to RE# low (data only)

 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the

 *	      rising edge of R/B#.

 * @tWB_max: WE# high to SR[6] low

 * @tWC_min: WE# cycle time

 * @tWH_min: WE# high hold time

 * @tWHR_min: WE# high to RE# low

 * @tWP_min: WE# pulse width

 * @tWW_min: WP# transition to WE# low

 */

struct nand_sdr_timings {

	u32 tALH_min;

	u32 tADL_min;

	u32 tALS_min;

	u32 tAR_min;

	u32 tCEA_max;

	u32 tCEH_min;

	u32 tCH_min;

	u32 tCHZ_max;

	u32 tCLH_min;

	u32 tCLR_min;

	u32 tCLS_min;

	u32 tCOH_min;

	u32 tCS_min;

	u32 tDH_min;

	u32 tDS_min;

	u32 tFEAT_max;

	u32 tIR_min;

	u32 tITC_max;

	u32 tRC_min;

	u32 tREA_max;

	u32 tREH_min;

	u32 tRHOH_min;

	u32 tRHW_min;

	u32 tRHZ_max;

	u32 tRLOH_min;

	u32 tRP_min;

	u32 tRR_min;

	u64 tRST_max;

	u32 tWB_max;

	u32 tWC_min;

	u32 tWH_min;

	u32 tWHR_min;

	u32 tWP_min;

	u32 tWW_min;

};



/**

 * enum nand_data_interface_type - NAND interface timing type

 * @NAND_SDR_IFACE:	Single Data Rate interface

 */

enum nand_data_interface_type {

	NAND_SDR_IFACE,

};



/**

 * struct nand_data_interface - NAND interface timing

 * @type:	type of the timing

 * @timings:	The timing, type according to @type

 */

struct nand_data_interface {

	enum nand_data_interface_type type;

	union {

		struct nand_sdr_timings sdr;

	} timings;

};



/**

 * nand_get_sdr_timings - get SDR timing from data interface

 * @conf:	The data interface

 */

static inline const struct nand_sdr_timings *

nand_get_sdr_timings(const struct nand_data_interface *conf)

{

	if (conf->type != NAND_SDR_IFACE)

		return ERR_PTR(-EINVAL);



	return &conf->timings.sdr;

}



/**

 * struct nand_chip - NAND Private Flash Chip Data

 * @mtd:		MTD device registered to the MTD framework
@@ -1030,55 +1147,6 @@ static inline int jedec_feature(struct nand_chip *chip) 
		: 0;

}



/*

 * struct nand_sdr_timings - SDR NAND chip timings

 *

 * This struct defines the timing requirements of a SDR NAND chip.

 * These informations can be found in every NAND datasheets and the timings

 * meaning are described in the ONFI specifications:

 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing

 * Parameters)

 *

 * All these timings are expressed in picoseconds.

 */



struct nand_sdr_timings {

	u32 tALH_min;

	u32 tADL_min;

	u32 tALS_min;

	u32 tAR_min;

	u32 tCEA_max;

	u32 tCEH_min;

	u32 tCH_min;

	u32 tCHZ_max;

	u32 tCLH_min;

	u32 tCLR_min;

	u32 tCLS_min;

	u32 tCOH_min;

	u32 tCS_min;

	u32 tDH_min;

	u32 tDS_min;

	u32 tFEAT_max;

	u32 tIR_min;

	u32 tITC_max;

	u32 tRC_min;

	u32 tREA_max;

	u32 tREH_min;

	u32 tRHOH_min;

	u32 tRHW_min;

	u32 tRHZ_max;

	u32 tRLOH_min;

	u32 tRP_min;

	u32 tRR_min;

	u64 tRST_max;

	u32 tWB_max;

	u32 tWC_min;

	u32 tWH_min;

	u32 tWHR_min;

	u32 tWP_min;

	u32 tWW_min;

};



/* get timing characteristics from ONFI timing mode. */

const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);