Loading drivers/power/supply/qcom/smb5-lib.c +42 −6 Original line number Diff line number Diff line Loading @@ -3426,19 +3426,55 @@ int smblib_set_prop_pr_swap_in_progress(struct smb_charger *chg, const union power_supply_propval *val) { int rc; u8 stat = 0, orientation; chg->pr_swap_in_progress = val->intval; /* * call the cc changed irq to handle real removals while * PR_SWAP was in progress */ smblib_usb_typec_change(chg); rc = smblib_masked_write(chg, TYPE_C_DEBOUNCE_OPTION_REG, REDUCE_TCCDEBOUNCE_TO_2MS_BIT, val->intval ? REDUCE_TCCDEBOUNCE_TO_2MS_BIT : 0); if (rc < 0) smblib_err(chg, "Couldn't set tCC debounce rc=%d\n", rc); rc = smblib_masked_write(chg, TYPE_C_EXIT_STATE_CFG_REG, BYPASS_VSAFE0V_DURING_ROLE_SWAP_BIT, val->intval ? BYPASS_VSAFE0V_DURING_ROLE_SWAP_BIT : 0); if (rc < 0) smblib_err(chg, "Couldn't set exit state cfg rc=%d\n", rc); if (chg->pr_swap_in_progress) { rc = smblib_read(chg, TYPE_C_MISC_STATUS_REG, &stat); if (rc < 0) { smblib_err(chg, "Couldn't read TYPE_C_STATUS_4 rc=%d\n", rc); } orientation = stat & CC_ORIENTATION_BIT ? TYPEC_CCOUT_VALUE_BIT : 0; rc = smblib_masked_write(chg, TYPE_C_CCOUT_CONTROL_REG, TYPEC_CCOUT_SRC_BIT | TYPEC_CCOUT_BUFFER_EN_BIT | TYPEC_CCOUT_VALUE_BIT, TYPEC_CCOUT_SRC_BIT | TYPEC_CCOUT_BUFFER_EN_BIT | orientation); if (rc < 0) { smblib_err(chg, "Couldn't read TYPE_C_CCOUT_CONTROL_REG rc=%d\n", rc); } } else { rc = smblib_masked_write(chg, TYPE_C_CCOUT_CONTROL_REG, TYPEC_CCOUT_SRC_BIT, 0); if (rc < 0) { smblib_err(chg, "Couldn't read TYPE_C_CCOUT_CONTROL_REG rc=%d\n", rc); } /* enable DRP */ rc = smblib_masked_write(chg, TYPE_C_MODE_CFG_REG, TYPEC_POWER_ROLE_CMD_MASK, 0); if (rc < 0) smblib_err(chg, "Couldn't enable DRP rc=%d\n", rc); } return 0; } Loading drivers/power/supply/qcom/smb5-reg.h +2 −0 Original line number Diff line number Diff line Loading @@ -287,10 +287,12 @@ enum { #define VCONN_EN_SRC_BIT BIT(0) #define TYPE_C_CCOUT_CONTROL_REG (TYPEC_BASE + 0x48) #define TYPEC_CCOUT_BUFFER_EN_BIT BIT(2) #define TYPEC_CCOUT_VALUE_BIT BIT(1) #define TYPEC_CCOUT_SRC_BIT BIT(0) #define TYPE_C_EXIT_STATE_CFG_REG (TYPEC_BASE + 0x50) #define BYPASS_VSAFE0V_DURING_ROLE_SWAP_BIT BIT(3) #define EXIT_SNK_BASED_ON_CC_BIT BIT(0) #define TYPE_C_INTERRUPT_EN_CFG_1_REG (TYPEC_BASE + 0x5E) Loading Loading
drivers/power/supply/qcom/smb5-lib.c +42 −6 Original line number Diff line number Diff line Loading @@ -3426,19 +3426,55 @@ int smblib_set_prop_pr_swap_in_progress(struct smb_charger *chg, const union power_supply_propval *val) { int rc; u8 stat = 0, orientation; chg->pr_swap_in_progress = val->intval; /* * call the cc changed irq to handle real removals while * PR_SWAP was in progress */ smblib_usb_typec_change(chg); rc = smblib_masked_write(chg, TYPE_C_DEBOUNCE_OPTION_REG, REDUCE_TCCDEBOUNCE_TO_2MS_BIT, val->intval ? REDUCE_TCCDEBOUNCE_TO_2MS_BIT : 0); if (rc < 0) smblib_err(chg, "Couldn't set tCC debounce rc=%d\n", rc); rc = smblib_masked_write(chg, TYPE_C_EXIT_STATE_CFG_REG, BYPASS_VSAFE0V_DURING_ROLE_SWAP_BIT, val->intval ? BYPASS_VSAFE0V_DURING_ROLE_SWAP_BIT : 0); if (rc < 0) smblib_err(chg, "Couldn't set exit state cfg rc=%d\n", rc); if (chg->pr_swap_in_progress) { rc = smblib_read(chg, TYPE_C_MISC_STATUS_REG, &stat); if (rc < 0) { smblib_err(chg, "Couldn't read TYPE_C_STATUS_4 rc=%d\n", rc); } orientation = stat & CC_ORIENTATION_BIT ? TYPEC_CCOUT_VALUE_BIT : 0; rc = smblib_masked_write(chg, TYPE_C_CCOUT_CONTROL_REG, TYPEC_CCOUT_SRC_BIT | TYPEC_CCOUT_BUFFER_EN_BIT | TYPEC_CCOUT_VALUE_BIT, TYPEC_CCOUT_SRC_BIT | TYPEC_CCOUT_BUFFER_EN_BIT | orientation); if (rc < 0) { smblib_err(chg, "Couldn't read TYPE_C_CCOUT_CONTROL_REG rc=%d\n", rc); } } else { rc = smblib_masked_write(chg, TYPE_C_CCOUT_CONTROL_REG, TYPEC_CCOUT_SRC_BIT, 0); if (rc < 0) { smblib_err(chg, "Couldn't read TYPE_C_CCOUT_CONTROL_REG rc=%d\n", rc); } /* enable DRP */ rc = smblib_masked_write(chg, TYPE_C_MODE_CFG_REG, TYPEC_POWER_ROLE_CMD_MASK, 0); if (rc < 0) smblib_err(chg, "Couldn't enable DRP rc=%d\n", rc); } return 0; } Loading
drivers/power/supply/qcom/smb5-reg.h +2 −0 Original line number Diff line number Diff line Loading @@ -287,10 +287,12 @@ enum { #define VCONN_EN_SRC_BIT BIT(0) #define TYPE_C_CCOUT_CONTROL_REG (TYPEC_BASE + 0x48) #define TYPEC_CCOUT_BUFFER_EN_BIT BIT(2) #define TYPEC_CCOUT_VALUE_BIT BIT(1) #define TYPEC_CCOUT_SRC_BIT BIT(0) #define TYPE_C_EXIT_STATE_CFG_REG (TYPEC_BASE + 0x50) #define BYPASS_VSAFE0V_DURING_ROLE_SWAP_BIT BIT(3) #define EXIT_SNK_BASED_ON_CC_BIT BIT(0) #define TYPE_C_INTERRUPT_EN_CFG_1_REG (TYPEC_BASE + 0x5E) Loading