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Commit ee7848eb authored by Pavan Kumar Chilamkurthi's avatar Pavan Kumar Chilamkurthi
Browse files

msm: camera: Change default clock voting level to SVS 



Select SVS level for clocks while enabling soc resources
to save power. Blocks such as IFE, IPE scale the clock
voting based on requirement dynamically and blocks such
as csiphy never need turbo clock.

Change-Id: I168a7e79ead0fd6c618b1d19d2d3b0e48a5f99c2
Signed-off-by: default avatarPavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
parent e250b1b2

drivers/media/platform/msm/camera/cam_icp/icp_hw/a5_hw/a5_core.c

+2 −2
Original line number Diff line number Diff line
@@ -266,8 +266,8 @@ int cam_a5_init_hw(void *device_priv, 


	cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE;

	cpas_vote.ahb_vote.vote.level = CAM_SVS_VOTE;

	cpas_vote.axi_vote.compressed_bw = ICP_TURBO_VOTE;

	cpas_vote.axi_vote.uncompressed_bw = ICP_TURBO_VOTE;

	cpas_vote.axi_vote.compressed_bw = CAM_ICP_A5_BW_BYTES_VOTE;

	cpas_vote.axi_vote.uncompressed_bw = CAM_ICP_A5_BW_BYTES_VOTE;



	rc = cam_cpas_start(core_info->cpas_handle,

		&cpas_vote.ahb_vote, &cpas_vote.axi_vote);

drivers/media/platform/msm/camera/cam_icp/icp_hw/a5_hw/a5_soc.c

+1 −1
Original line number Diff line number Diff line
@@ -101,7 +101,7 @@ int cam_a5_enable_soc_resources(struct cam_hw_soc_info *soc_info) 
	int rc = 0;



	rc = cam_soc_util_enable_platform_resource(soc_info, true,

		CAM_TURBO_VOTE, true);

		CAM_SVS_VOTE, true);

	if (rc)

		CAM_ERR(CAM_ICP, "enable platform failed");

drivers/media/platform/msm/camera/cam_icp/icp_hw/bps_hw/bps_soc.c

+1 −1
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ int cam_bps_enable_soc_resources(struct cam_hw_soc_info *soc_info) 
	int rc = 0;



	rc = cam_soc_util_enable_platform_resource(soc_info, true,

		CAM_TURBO_VOTE, false);

		CAM_SVS_VOTE, false);

	if (rc)

		CAM_ERR(CAM_ICP, "enable platform failed");

drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c

+6 −6
Original line number Diff line number Diff line
@@ -95,13 +95,13 @@ static void cam_icp_hw_mgr_reset_clk_info(struct cam_icp_hw_mgr *hw_mgr) 


	for (i = 0; i < ICP_CLK_HW_MAX; i++) {

		hw_mgr->clk_info[i].base_clk = 0;

		hw_mgr->clk_info[i].curr_clk = ICP_TURBO_VOTE;

		hw_mgr->clk_info[i].curr_clk = ICP_CLK_SVS_HZ;

		hw_mgr->clk_info[i].threshold = ICP_OVER_CLK_THRESHOLD;

		hw_mgr->clk_info[i].over_clked = 0;

		hw_mgr->clk_info[i].uncompressed_bw = CAM_CPAS_DEFAULT_AXI_BW;

		hw_mgr->clk_info[i].compressed_bw = CAM_CPAS_DEFAULT_AXI_BW;

	}

	hw_mgr->icp_default_clk = ICP_SVS_VOTE;

	hw_mgr->icp_default_clk = ICP_CLK_SVS_HZ;

}



static int cam_icp_get_actual_clk_rate_idx(
@@ -231,14 +231,14 @@ static int cam_icp_clk_info_init(struct cam_icp_hw_mgr *hw_mgr, 
	int i;



	for (i = 0; i < ICP_CLK_HW_MAX; i++) {

		hw_mgr->clk_info[i].base_clk = ICP_TURBO_VOTE;

		hw_mgr->clk_info[i].curr_clk = ICP_TURBO_VOTE;

		hw_mgr->clk_info[i].base_clk = ICP_CLK_SVS_HZ;

		hw_mgr->clk_info[i].curr_clk = ICP_CLK_SVS_HZ;

		hw_mgr->clk_info[i].threshold = ICP_OVER_CLK_THRESHOLD;

		hw_mgr->clk_info[i].over_clked = 0;

		hw_mgr->clk_info[i].uncompressed_bw = CAM_CPAS_DEFAULT_AXI_BW;

		hw_mgr->clk_info[i].compressed_bw = CAM_CPAS_DEFAULT_AXI_BW;

	}

	hw_mgr->icp_default_clk = ICP_SVS_VOTE;

	hw_mgr->icp_default_clk = ICP_CLK_SVS_HZ;



	return 0;

}
@@ -466,7 +466,7 @@ static bool cam_icp_update_clk_free(struct cam_icp_hw_mgr *hw_mgr, 


static bool cam_icp_debug_clk_update(struct cam_icp_clk_info *hw_mgr_clk_info)

{

	if (icp_hw_mgr.icp_debug_clk < ICP_TURBO_VOTE &&

	if (icp_hw_mgr.icp_debug_clk < ICP_CLK_TURBO_HZ &&

		icp_hw_mgr.icp_debug_clk &&

		icp_hw_mgr.icp_debug_clk != hw_mgr_clk_info->curr_clk) {

		mutex_lock(&icp_hw_mgr.hw_mgr_mutex);

drivers/media/platform/msm/camera/cam_icp/icp_hw/include/cam_icp_hw_mgr_intf.h

+5 −2
Original line number Diff line number Diff line
@@ -18,8 +18,11 @@ 
#include <linux/of.h>

#include "cam_cpas_api.h"



#define ICP_TURBO_VOTE           600000000

#define ICP_SVS_VOTE             400000000

#define ICP_CLK_TURBO_HZ         600000000

#define ICP_CLK_SVS_HZ           400000000



#define CAM_ICP_A5_BW_BYTES_VOTE 100000000



#define CAM_ICP_CTX_MAX          36



#define CPAS_IPE1_BIT            0x2000