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Commit ee3b93eb authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/mm: Move hash64 tlbflush code into a new header 



No code changes.

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent f64e8084

arch/powerpc/include/asm/book3s/64/tlbflush-hash.h

0 → 100644
+94 −0
Original line number Diff line number Diff line 
#ifndef _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H

#define _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H



#define MMU_NO_CONTEXT		0



/*

 * TLB flushing for 64-bit hash-MMU CPUs

 */



#include <linux/percpu.h>

#include <asm/page.h>



#define PPC64_TLB_BATCH_NR 192



struct ppc64_tlb_batch {

	int			active;

	unsigned long		index;

	struct mm_struct	*mm;

	real_pte_t		pte[PPC64_TLB_BATCH_NR];

	unsigned long		vpn[PPC64_TLB_BATCH_NR];

	unsigned int		psize;

	int			ssize;

};

DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);



extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);



#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE



static inline void arch_enter_lazy_mmu_mode(void)

{

	struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);



	batch->active = 1;

}



static inline void arch_leave_lazy_mmu_mode(void)

{

	struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);



	if (batch->index)

		__flush_tlb_pending(batch);

	batch->active = 0;

}



#define arch_flush_lazy_mmu_mode()      do {} while (0)





extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize,

			    int ssize, unsigned long flags);

extern void flush_hash_range(unsigned long number, int local);

extern void flush_hash_hugepage(unsigned long vsid, unsigned long addr,

				pmd_t *pmdp, unsigned int psize, int ssize,

				unsigned long flags);



static inline void local_flush_tlb_mm(struct mm_struct *mm)

{

}



static inline void flush_tlb_mm(struct mm_struct *mm)

{

}



static inline void local_flush_tlb_page(struct vm_area_struct *vma,

					unsigned long vmaddr)

{

}



static inline void flush_tlb_page(struct vm_area_struct *vma,

				  unsigned long vmaddr)

{

}



static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,

					 unsigned long vmaddr)

{

}



static inline void flush_tlb_range(struct vm_area_struct *vma,

				   unsigned long start, unsigned long end)

{

}



static inline void flush_tlb_kernel_range(unsigned long start,

					  unsigned long end)

{

}



/* Private function for use by PCI IO mapping code */

extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,

				     unsigned long end);

extern void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd,

				unsigned long addr);

#endif /*  _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H */

arch/powerpc/include/asm/tlbflush.h

+1 −91
Original line number Diff line number Diff line
@@ -78,97 +78,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) 
}



#elif defined(CONFIG_PPC_STD_MMU_64)



#define MMU_NO_CONTEXT		0



/*

 * TLB flushing for 64-bit hash-MMU CPUs

 */



#include <linux/percpu.h>

#include <asm/page.h>



#define PPC64_TLB_BATCH_NR 192



struct ppc64_tlb_batch {

	int			active;

	unsigned long		index;

	struct mm_struct	*mm;

	real_pte_t		pte[PPC64_TLB_BATCH_NR];

	unsigned long		vpn[PPC64_TLB_BATCH_NR];

	unsigned int		psize;

	int			ssize;

};

DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);



extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);



#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE



static inline void arch_enter_lazy_mmu_mode(void)

{

	struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);



	batch->active = 1;

}



static inline void arch_leave_lazy_mmu_mode(void)

{

	struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);



	if (batch->index)

		__flush_tlb_pending(batch);

	batch->active = 0;

}



#define arch_flush_lazy_mmu_mode()      do {} while (0)





extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize,

			    int ssize, unsigned long flags);

extern void flush_hash_range(unsigned long number, int local);

extern void flush_hash_hugepage(unsigned long vsid, unsigned long addr,

				pmd_t *pmdp, unsigned int psize, int ssize,

				unsigned long flags);



static inline void local_flush_tlb_mm(struct mm_struct *mm)

{

}



static inline void flush_tlb_mm(struct mm_struct *mm)

{

}



static inline void local_flush_tlb_page(struct vm_area_struct *vma,

					unsigned long vmaddr)

{

}



static inline void flush_tlb_page(struct vm_area_struct *vma,

				  unsigned long vmaddr)

{

}



static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,

					 unsigned long vmaddr)

{

}



static inline void flush_tlb_range(struct vm_area_struct *vma,

				   unsigned long start, unsigned long end)

{

}



static inline void flush_tlb_kernel_range(unsigned long start,

					  unsigned long end)

{

}



/* Private function for use by PCI IO mapping code */

extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,

				     unsigned long end);

extern void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd,

				unsigned long addr);

#include <asm/book3s/64/tlbflush-hash.h>

#else

#error Unsupported MMU type

#endif