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Commit ee1d06bc authored by Kyle Yan's avatar Kyle Yan Committed by Gerrit - the friendly Code Review server
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Merge "clk: mdss: fix pll 1 leakage issue by calling power down sequence" into msm-4.8

parents 65eab40d ffb69645

drivers/clk/qcom/mdss/mdss-dsi-20nm-pll-util.c

+15 −16
Original line number Diff line number Diff line
@@ -500,6 +500,19 @@ void __dsi_pll_disable(void __iomem *pll_base) 
	MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_RESETSM_CNTRL3, 0x06);

}



static void pll_20nm_config_powerdown(void __iomem *pll_base)

{

	if (!pll_base) {

		pr_err("Invalid pll base.\n");

		return;

	}



	MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_SYS_CLK_CTRL, 0x00);

	MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_CMN_MODE, 0x01);

	MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN, 0x82);

	MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN, 0x02);

}



static int dsi_pll_enable(struct clk *c)

{

	int i, rc;
@@ -522,7 +535,7 @@ static int dsi_pll_enable(struct clk *c) 
	}

	/* Disable PLL1 to avoid current leakage while toggling MDSS GDSC */

	if (dsi_pll_res->pll_1_base)

		__dsi_pll_disable(dsi_pll_res->pll_1_base);

		pll_20nm_config_powerdown(dsi_pll_res->pll_1_base);



	if (rc) {

		mdss_pll_resource_enable(dsi_pll_res, false);
@@ -533,20 +546,6 @@ static int dsi_pll_enable(struct clk *c) 
	return rc;

}





static void pll_20nm_config_powerdown(void __iomem *pll_base)

{

	if (!pll_base) {

		pr_err("Invalid pll base.\n");

		return;

	}



	MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_SYS_CLK_CTRL, 0x00);

	MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_CMN_MODE, 0x01);

	MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN, 0x82);

	MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN, 0x02);

}



static void dsi_pll_disable(struct clk *c)

{

	struct dsi_pll_vco_clk *vco = to_vco_clk(c);
@@ -564,7 +563,7 @@ static void dsi_pll_disable(struct clk *c) 


	/* Disable PLL1 to avoid current leakage while toggling MDSS GDSC */

	if (dsi_pll_res->pll_1_base)

		__dsi_pll_disable(dsi_pll_res->pll_1_base);

		pll_20nm_config_powerdown(dsi_pll_res->pll_1_base);



	pll_20nm_config_powerdown(dsi_pll_res->pll_base);