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Commit ed8bc7ed authored by Ingo Molnar's avatar Ingo Molnar Committed by H. Peter Anvin
Browse files

x86, mce: clean up p5.c 



Make the coding style match that of the rest of the x86 arch code.

[ Impact: cleanup ]

Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent c5aaf0e0

arch/x86/kernel/cpu/mcheck/p5.c

+28 −15
Original line number Diff line number Diff line
@@ -2,11 +2,10 @@ 
 * P5 specific Machine Check Exception Reporting

 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>

 */



#include <linux/init.h>

#include <linux/types.h>

#include <linux/kernel.h>

#include <linux/interrupt.h>

#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/init.h>

#include <linux/smp.h>



#include <asm/processor.h>
@@ -15,39 +14,53 @@ 


#include "mce.h"



/* Machine check handler for Pentium class Intel */

/* Machine check handler for Pentium class Intel CPUs: */

static void pentium_machine_check(struct pt_regs *regs, long error_code)

{

	u32 loaddr, hi, lotype;



	rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);

	rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);

	printk(KERN_EMERG "CPU#%d: Machine Check Exception:  0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype);

	if (lotype&(1<<5))

		printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id());



	printk(KERN_EMERG

		"CPU#%d: Machine Check Exception:  0x%8X (type 0x%8X).\n",

		smp_processor_id(), loaddr, lotype);



	if (lotype & (1<<5)) {

		printk(KERN_EMERG

			"CPU#%d: Possible thermal failure (CPU on fire ?).\n",

			smp_processor_id());

	}



	add_taint(TAINT_MACHINE_CHECK);

}



/* Set up machine check reporting for processors with Intel style MCE */

/* Set up machine check reporting for processors with Intel style MCE: */

void intel_p5_mcheck_init(struct cpuinfo_x86 *c)

{

	u32 l, h;



	/*Check for MCE support */

	/* Check for MCE support: */

	if (!cpu_has(c, X86_FEATURE_MCE))

		return;



	/* Default P5 to off as its often misconnected */

	/* Default P5 to off as its often misconnected: */

	if (mce_disabled != -1)

		return;



	machine_check_vector = pentium_machine_check;

	/* Make sure the vector pointer is visible before we enable MCEs: */

	wmb();



	/* Read registers before enabling */

	/* Read registers before enabling: */

	rdmsr(MSR_IA32_P5_MC_ADDR, l, h);

	rdmsr(MSR_IA32_P5_MC_TYPE, l, h);

	printk(KERN_INFO "Intel old style machine check architecture supported.\n");

	printk(KERN_INFO

	       "Intel old style machine check architecture supported.\n");



	/* Enable MCE */

	/* Enable MCE: */

	set_in_cr4(X86_CR4_MCE);

	printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id());

	printk(KERN_INFO

	       "Intel old style machine check reporting enabled on CPU#%d.\n",

	       smp_processor_id());

}