Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ed6f4b51 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Kevin Hilman
Browse files

clk: gxbb: expose MPLL2 clock for use by DT



This exposes the MPLL2 clock as this is one of the input clocks of the
ethernet controller's internal mux.

Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent dcdcc660
Loading
Loading
Loading
Loading
+1 −1
Original line number Diff line number Diff line
@@ -183,7 +183,7 @@
/* CLKID_CLK81 */
#define CLKID_MPLL0		  13
#define CLKID_MPLL1		  14
#define CLKID_MPLL2		  15
/* CLKID_MPLL2 */
#define CLKID_DDR		  16
#define CLKID_DOS		  17
#define CLKID_ISA		  18
+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@
#define CLKID_FCLK_DIV3		5
#define CLKID_FCLK_DIV4		6
#define CLKID_CLK81		12
#define CLKID_MPLL2		15
#define CLKID_ETH		36
#define CLKID_SD_EMMC_A		94
#define CLKID_SD_EMMC_B		95