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Commit ecb988a3 authored by Steve Shih's avatar Steve Shih Committed by Greg Kroah-Hartman
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tty: serial: 8250: 8250_core: NXP SC16C2552 workaround 



NXP SC16C2552 requires that we always write a reset to the RX FIFO and
TX FIFO whenever we enable the FIFOs

Cc: xe-kernel@external.cisco.com
Signed-off-by: default avatarSteve Shih <sshih@cisco.com>
Signed-off-by: default avatarDavid Singleton <davsingl@cisco.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 32b2921e

drivers/tty/serial/8250/8250_port.c

+2 −1
Original line number Diff line number Diff line
@@ -83,7 +83,8 @@ static const struct serial8250_config uart_config[] = { 
		.name		= "16550A",

		.fifo_size	= 16,

		.tx_loadsz	= 16,

		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,

		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |

				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,

		.rxtrig_bytes	= {1, 4, 8, 14},

		.flags		= UART_CAP_FIFO,

	},