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Commit ec752def authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Enable the A6XX power counter" into msm-4.9

parents e098b4b4 856ca606

drivers/gpu/msm/a6xx_reg.h

+5 −0
Original line number Diff line number Diff line
@@ -796,6 +796,10 @@ 
#define A6XX_GMU_CM3_FW_BUSY			0x1F81A

#define A6XX_GMU_CM3_FW_INIT_RESULT		0x1F81C

#define A6XX_GMU_CM3_CFG			0x1F82D

#define A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE	0x1F840

#define A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0	0x1F841

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L	0x1F844

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H	0x1F845

#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL	0x1F8C0

#define A6XX_GMU_PWR_COL_INTER_FRAME_HYST	0x1F8C1

#define A6XX_GMU_PWR_COL_SPTPRAC_HYST		0x1F8C2
@@ -848,6 +852,7 @@ 
#define A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL      0x23B0A

#define A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL       0x23B0B

#define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS	0x23B0C

#define A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK	0x23B0E

#define A6XX_GMU_AHB_FENCE_STATUS		0x23B13

#define A6XX_GMU_RBBM_INT_UNMASKED_STATUS	0x23B15

#define A6XX_GMU_AO_SPARE_CNTL			0x23B16

drivers/gpu/msm/adreno_a6xx.c

+34 −0
Original line number Diff line number Diff line
@@ -2419,6 +2419,13 @@ static struct adreno_perfcount_register a6xx_perfcounters_vbif_pwr[] = { 
		A6XX_VBIF_PERF_PWR_CNT_HIGH2, -1, A6XX_VBIF_PERF_PWR_CNT_EN2 },

};



static struct adreno_perfcount_register a6xx_perfcounters_pwr[] = {

	{ KGSL_PERFCOUNTER_BROKEN, 0, 0, 0, 0, -1, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,

		A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H, -1, 0 },

};



static struct adreno_perfcount_register a6xx_perfcounters_alwayson[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_CP_ALWAYS_ON_COUNTER_LO,

		A6XX_CP_ALWAYS_ON_COUNTER_HI, -1 },
@@ -2451,6 +2458,8 @@ static struct adreno_perfcount_group a6xx_perfcounter_groups 
	A6XX_PERFCOUNTER_GROUP(VBIF, vbif),

	A6XX_PERFCOUNTER_GROUP_FLAGS(VBIF_PWR, vbif_pwr,

		ADRENO_PERFCOUNTER_GROUP_FIXED),

	A6XX_PERFCOUNTER_GROUP_FLAGS(PWR, pwr,

		ADRENO_PERFCOUNTER_GROUP_FIXED),

	A6XX_PERFCOUNTER_GROUP_FLAGS(ALWAYSON, alwayson,

		ADRENO_PERFCOUNTER_GROUP_FIXED),

};
@@ -2460,6 +2469,30 @@ static struct adreno_perfcounters a6xx_perfcounters = { 
	ARRAY_SIZE(a6xx_perfcounter_groups),

};



/* Program the GMU power counter to count GPU busy cycles */

static int a6xx_enable_pwr_counters(struct adreno_device *adreno_dev,

		unsigned int counter)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	/*

	 * We have a limited number of power counters. Since we're not using

	 * total GPU cycle count, return error if requested.

	 */

	if (counter == 0)

		return -EINVAL;



	if (!device->gmu.pdev)

		return -ENODEV;



	kgsl_regwrite(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0);

	kgsl_regrmw(device,

		A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xFF, 0x20);

	kgsl_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0x1);



	return 0;

}



/* Register offset defines for A6XX, in order of enum adreno_regs */

static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
@@ -2581,6 +2614,7 @@ struct adreno_gpudev adreno_a6xx_gpudev = { 
	.regulator_enable = a6xx_sptprac_enable,

	.regulator_disable = a6xx_sptprac_disable,

	.perfcounters = &a6xx_perfcounters,

	.enable_pwr_counters = a6xx_enable_pwr_counters,

	.microcode_read = a6xx_microcode_read,

	.enable_64bit = a6xx_enable_64bit,

	.llc_configure_gpu_scid = a6xx_llc_configure_gpu_scid,