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Commit ebc3319d authored by Amit Nischal's avatar Amit Nischal
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clk: qcom: Add support to export clk_rcg2_calc_rate() 



There could be some use cases where clk_rcg2_calc_rate()
needs to be use in other modules for calculating rate, so
add support for the same by exporting it as kernel symbol.

Change-Id: If0840f3f2759d97c99bf3d06e3caf91d9a0ede73
Signed-off-by: default avatarAmit Nischal <anischal@codeaurora.org>
parent 87b21110

drivers/clk/qcom/clk-rcg.h

+2 −0
Original line number Diff line number Diff line
@@ -188,4 +188,6 @@ extern const struct clk_ops clk_dp_ops; 


extern int clk_rcg2_get_dfs_clock_rate(struct clk_rcg2 *clk,

				struct device *dev, u8 rcg_flags);

extern unsigned long

clk_rcg2_calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div);

#endif

drivers/clk/qcom/clk-rcg2.c

+8 −7
Original line number Diff line number Diff line
@@ -223,8 +223,8 @@ static void disable_unprepare_rcg_srcs(struct clk *curr, struct clk *new) 
 *   rate = ----------- x  ---

 *            hid_div       n

 */

static unsigned long

calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)

unsigned long

clk_rcg2_calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)

{

	if (hid_div) {

		rate *= 2;
@@ -240,6 +240,7 @@ calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) 


	return rate;

}

EXPORT_SYMBOL(clk_rcg2_calc_rate);



static unsigned long

clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
@@ -274,7 +275,7 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
	hid_div = cfg >> CFG_SRC_DIV_SHIFT;

	hid_div &= mask;



	return calc_rate(parent_rate, m, n, mode, hid_div);

	return clk_rcg2_calc_rate(parent_rate, m, n, mode, hid_div);

}



static int _freq_tbl_determine_rate(struct clk_hw *hw,
@@ -764,7 +765,7 @@ static int clk_edp_pixel_determine_rate(struct clk_hw *hw, 
		hid_div >>= CFG_SRC_DIV_SHIFT;

		hid_div &= mask;



		req->rate = calc_rate(req->best_parent_rate,

		req->rate = clk_rcg2_calc_rate(req->best_parent_rate,

				      frac->num, frac->den,

				      !!frac->den, hid_div);

		return 0;
@@ -804,7 +805,7 @@ static int clk_byte_determine_rate(struct clk_hw *hw, 
	div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1;

	div = min_t(u32, div, mask);



	req->rate = calc_rate(parent_rate, 0, 0, 0, div);

	req->rate = clk_rcg2_calc_rate(parent_rate, 0, 0, 0, div);



	return 0;

}
@@ -862,7 +863,7 @@ static int clk_byte2_determine_rate(struct clk_hw *hw, 
	div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;

	div = min_t(u32, div, mask);



	req->rate = calc_rate(parent_rate, 0, 0, 0, div);

	req->rate = clk_rcg2_calc_rate(parent_rate, 0, 0, 0, div);



	return 0;

}
@@ -1318,7 +1319,7 @@ int clk_rcg2_get_dfs_clock_rate(struct clk_rcg2 *clk, struct device *dev, 
		dfs_freq_tbl[i].n = n;



		/* calculate the final frequency */

		calc_freq = calc_rate(prate, dfs_freq_tbl[i].m,

		calc_freq = clk_rcg2_calc_rate(prate, dfs_freq_tbl[i].m,

						dfs_freq_tbl[i].n, mode,

						dfs_freq_tbl[i].pre_div);