Merge "clk: mdss: shadow clock implementation for dynamic refresh rate" into msm-4.8 (eb7b835d) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/clk/qcom/mdss/mdss-dsi-pll-8996-util.c

+186 −0

Original line number	Original line	Diff line number	Diff line
	@@ -48,6 +48,52 @@ int get_mdss_pixel_mux_sel_8996(struct mux_clk *clk)
	return 0;		return 0;
	}		}

			static int mdss_pll_read_stored_trim_codes(
			struct mdss_pll_resources *dsi_pll_res, s64 vco_clk_rate)
			{
			int i;
			int rc = 0;
			bool found = false;

			if (!dsi_pll_res->dfps) {
			rc = -EINVAL;
			goto end_read;
			}

			for (i = 0; i < dsi_pll_res->dfps->panel_dfps.frame_rate_cnt; i++) {
			struct dfps_codes_info *codes_info =
			&dsi_pll_res->dfps->codes_dfps[i];

			pr_debug("valid=%d frame_rate=%d, vco_rate=%d, code %d %d\n",
			codes_info->is_valid, codes_info->frame_rate,
			codes_info->clk_rate, codes_info->pll_codes.pll_codes_1,
			codes_info->pll_codes.pll_codes_2);

			if (vco_clk_rate != codes_info->clk_rate &&
			codes_info->is_valid)
			continue;

			dsi_pll_res->cache_pll_trim_codes[0] =
			codes_info->pll_codes.pll_codes_1;
			dsi_pll_res->cache_pll_trim_codes[1] =
			codes_info->pll_codes.pll_codes_2;
			found = true;
			break;
			}

			if (!found) {
			rc = -EINVAL;
			goto end_read;
			}

			pr_debug("core_kvco_code=0x%x core_vco_tune=0x%x\n",
			dsi_pll_res->cache_pll_trim_codes[0],
			dsi_pll_res->cache_pll_trim_codes[1]);

			end_read:
			return rc;
			}

	int post_n1_div_set_div(struct div_clk *clk, int div)		int post_n1_div_set_div(struct div_clk *clk, int div)
	{		{
	struct mdss_pll_resources *pll = clk->priv;		struct mdss_pll_resources *pll = clk->priv;
	@@ -148,6 +194,26 @@ int n2_div_set_div(struct div_clk *clk, int div)
	return rc;		return rc;
	}		}

			int shadow_n2_div_set_div(struct div_clk *clk, int div)
			{
			struct mdss_pll_resources *pll = clk->priv;
			struct dsi_pll_db *pdb;
			struct dsi_pll_output *pout;
			u32 data;

			pdb = pll->priv;
			pout = &pdb->out;

			pout->pll_n2div = div;

			data = (pout->pll_n1div \| (pout->pll_n2div << 4));
			MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_CTRL19,
			DSIPHY_CMN_CLK_CFG0, DSIPHY_CMN_CLK_CFG1,
			data, 1);
			return 0;
			}

	int n2_div_get_div(struct div_clk *clk)		int n2_div_get_div(struct div_clk *clk)
	{		{
	int rc;		int rc;
	@@ -791,6 +857,121 @@ int pll_vco_set_rate_8996(struct clk *c, unsigned long rate)
	return rc;		return rc;
	}		}

			static void shadow_pll_dynamic_refresh_8996(struct mdss_pll_resources *pll,
			struct dsi_pll_db *pdb)
			{
			struct dsi_pll_output *pout = &pdb->out;

			MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_CTRL20,
			DSIPHY_CMN_CTRL_0, DSIPHY_PLL_SYSCLK_EN_RESET,
			0xFF, 0x0);
			MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_CTRL21,
			DSIPHY_PLL_DEC_START, DSIPHY_PLL_DIV_FRAC_START1,
			pout->dec_start, (pout->div_frac_start & 0x0FF));
			MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_CTRL22,
			DSIPHY_PLL_DIV_FRAC_START2, DSIPHY_PLL_DIV_FRAC_START3,
			((pout->div_frac_start >> 8) & 0x0FF),
			((pout->div_frac_start >> 16) & 0x0F));
			MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_CTRL23,
			DSIPHY_PLL_PLLLOCK_CMP1, DSIPHY_PLL_PLLLOCK_CMP2,
			(pout->plllock_cmp & 0x0FF),
			((pout->plllock_cmp >> 8) & 0x0FF));
			MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_CTRL24,
			DSIPHY_PLL_PLLLOCK_CMP3, DSIPHY_PLL_PLL_VCO_TUNE,
			((pout->plllock_cmp >> 16) & 0x03),
			(pll->cache_pll_trim_codes[1] \| BIT(7))); /* VCO tune*/
			MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_CTRL25,
			DSIPHY_PLL_KVCO_CODE, DSIPHY_PLL_RESETSM_CNTRL,
			(pll->cache_pll_trim_codes[0] \| BIT(5)), 0x38);
			MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_CTRL26,
			DSIPHY_PLL_PLL_LPF2_POSTDIV, DSIPHY_CMN_PLL_CNTRL,
			(((pout->pll_postdiv - 1) << 4) \| pdb->in.pll_lpf_res1), 0x01);
			MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_CTRL27,
			DSIPHY_CMN_PLL_CNTRL, DSIPHY_CMN_PLL_CNTRL,
			0x01, 0x01);
			MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_CTRL28,
			DSIPHY_CMN_PLL_CNTRL, DSIPHY_CMN_PLL_CNTRL,
			0x01, 0x01);
			MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_CTRL29,
			DSIPHY_CMN_PLL_CNTRL, DSIPHY_CMN_PLL_CNTRL,
			0x01, 0x01);
			MDSS_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR, 0x0000001E);
			MDSS_PLL_REG_W(pll->dyn_pll_base,
			DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2, 0x003FFE00);

			/*
			* Ensure all the dynamic refresh registers are written before
			* dynamic refresh to change the fps is triggered
			*/
			wmb();
			}

			int shadow_pll_vco_set_rate_8996(struct clk *c, unsigned long rate)
			{
			int rc;
			struct dsi_pll_vco_clk *vco = to_vco_clk(c);
			struct mdss_pll_resources *pll = vco->priv;
			struct dsi_pll_db *pdb;
			s64 vco_clk_rate = (s64)rate;

			if (!pll) {
			pr_err("PLL data not found\n");
			return -EINVAL;
			}

			pdb = pll->priv;
			if (!pdb) {
			pr_err("No priv data found\n");
			return -EINVAL;
			}

			rc = mdss_pll_read_stored_trim_codes(pll, vco_clk_rate);
			if (rc) {
			pr_err("cannot find pll codes rate=%lld\n", vco_clk_rate);
			return -EINVAL;
			}

			rc = mdss_pll_resource_enable(pll, true);
			if (rc) {
			pr_err("Failed to enable mdss dsi plla=%d\n", pll->index);
			return rc;
			}

			pr_debug("%s: ndx=%d base=%p rate=%lu\n", __func__,
			pll->index, pll->pll_base, rate);

			pll->vco_current_rate = rate;
			pll->vco_ref_clk_rate = vco->ref_clk_rate;

			mdss_dsi_pll_8996_input_init(pll, pdb);

			pll_8996_dec_frac_calc(pll, pdb);

			pll_8996_calc_vco_count(pdb, pll->vco_current_rate,
			pll->vco_ref_clk_rate);

			shadow_pll_dynamic_refresh_8996(pll, pdb);

			rc = mdss_pll_resource_enable(pll, false);
			if (rc) {
			pr_err("Failed to enable mdss dsi plla=%d\n", pll->index);
			return rc;
			}

			return rc;
			}

	unsigned long pll_vco_get_rate_8996(struct clk *c)		unsigned long pll_vco_get_rate_8996(struct clk *c)
	{		{
	u64 vco_rate, multiplier = BIT(20);		u64 vco_rate, multiplier = BIT(20);
	@@ -882,6 +1063,11 @@ enum handoff pll_vco_handoff_8996(struct clk *c)
	return ret;		return ret;
	}		}

			enum handoff shadow_pll_vco_handoff_8996(struct clk *c)
			{
			return HANDOFF_DISABLED_CLK;
			}

	int pll_vco_prepare_8996(struct clk *c)		int pll_vco_prepare_8996(struct clk *c)
	{		{
	int rc = 0;		int rc = 0;

drivers/clk/qcom/mdss/mdss-dsi-pll-8996.c

+201 −8

Original line number	Original line	Diff line number	Diff line
	@@ -31,8 +31,10 @@
	static struct dsi_pll_db pll_db[DSI_PLL_NUM];		static struct dsi_pll_db pll_db[DSI_PLL_NUM];

	static const struct clk_ops n2_clk_src_ops;		static const struct clk_ops n2_clk_src_ops;
			static const struct clk_ops shadow_n2_clk_src_ops;
	static const struct clk_ops byte_clk_src_ops;		static const struct clk_ops byte_clk_src_ops;
	static const struct clk_ops post_n1_div_clk_src_ops;		static const struct clk_ops post_n1_div_clk_src_ops;
			static const struct clk_ops shadow_post_n1_div_clk_src_ops;

	static const struct clk_ops clk_ops_gen_mux_dsi;		static const struct clk_ops clk_ops_gen_mux_dsi;

	@@ -65,6 +67,21 @@ static struct clk_mux_ops mdss_pixel_mux_ops = {
	.get_mux_sel = get_mdss_pixel_mux_sel_8996,		.get_mux_sel = get_mdss_pixel_mux_sel_8996,
	};		};

			/* Shadow ops for dynamic refresh */
			static const struct clk_ops clk_ops_shadow_dsi_vco = {
			.set_rate = shadow_pll_vco_set_rate_8996,
			.round_rate = pll_vco_round_rate_8996,
			.handoff = shadow_pll_vco_handoff_8996,
			};

			static struct clk_div_ops shadow_post_n1_div_ops = {
			.set_div = post_n1_div_set_div,
			};

			static struct clk_div_ops shadow_n2_div_ops = {
			.set_div = shadow_n2_div_set_div,
			};

	static struct dsi_pll_vco_clk dsi0pll_vco_clk = {		static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
	.ref_clk_rate = 19200000,		.ref_clk_rate = 19200000,
	.min_rate = 1300000000,		.min_rate = 1300000000,
	@@ -78,6 +95,17 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
	},		},
	};		};

			static struct dsi_pll_vco_clk dsi0pll_shadow_vco_clk = {
			.ref_clk_rate = 19200000u,
			.min_rate = 1300000000u,
			.max_rate = 2600000000u,
			.c = {
			.dbg_name = "dsi0pll_shadow_vco_clk",
			.ops = &clk_ops_shadow_dsi_vco,
			CLK_INIT(dsi0pll_shadow_vco_clk.c),
			},
			};

	static struct dsi_pll_vco_clk dsi1pll_vco_clk = {		static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
	.ref_clk_rate = 19200000,		.ref_clk_rate = 19200000,
	.min_rate = 1300000000,		.min_rate = 1300000000,
	@@ -91,6 +119,19 @@ static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
	},		},
	};		};

			static struct dsi_pll_vco_clk dsi1pll_shadow_vco_clk = {
			.ref_clk_rate = 19200000u,
			.min_rate = 1300000000u,
			.max_rate = 2600000000u,
			.pll_en_seq_cnt = 1,
			.pll_enable_seqs[0] = dsi_pll_enable_seq_8996,
			.c = {
			.dbg_name = "dsi1pll_shadow_vco_clk",
			.ops = &clk_ops_shadow_dsi_vco,
			CLK_INIT(dsi1pll_shadow_vco_clk.c),
			},
			};

	static struct div_clk dsi0pll_post_n1_div_clk = {		static struct div_clk dsi0pll_post_n1_div_clk = {
	.data = {		.data = {
	.max_div = 15,		.max_div = 15,
	@@ -106,6 +147,21 @@ static struct div_clk dsi0pll_post_n1_div_clk = {
	},		},
	};		};

			static struct div_clk dsi0pll_shadow_post_n1_div_clk = {
			.data = {
			.max_div = 15,
			.min_div = 1,
			},
			.ops = &shadow_post_n1_div_ops,
			.c = {
			.parent = &dsi0pll_shadow_vco_clk.c,
			.dbg_name = "dsi0pll_shadow_post_n1_div_clk",
			.ops = &shadow_post_n1_div_clk_src_ops,
			.flags = CLKFLAG_NO_RATE_CACHE,
			CLK_INIT(dsi0pll_shadow_post_n1_div_clk.c),
			},
			};

	static struct div_clk dsi1pll_post_n1_div_clk = {		static struct div_clk dsi1pll_post_n1_div_clk = {
	.data = {		.data = {
	.max_div = 15,		.max_div = 15,
	@@ -121,6 +177,21 @@ static struct div_clk dsi1pll_post_n1_div_clk = {
	},		},
	};		};

			static struct div_clk dsi1pll_shadow_post_n1_div_clk = {
			.data = {
			.max_div = 15,
			.min_div = 1,
			},
			.ops = &shadow_post_n1_div_ops,
			.c = {
			.parent = &dsi1pll_shadow_vco_clk.c,
			.dbg_name = "dsi1pll_shadow_post_n1_div_clk",
			.ops = &shadow_post_n1_div_clk_src_ops,
			.flags = CLKFLAG_NO_RATE_CACHE,
			CLK_INIT(dsi1pll_shadow_post_n1_div_clk.c),
			},
			};

	static struct div_clk dsi0pll_n2_div_clk = {		static struct div_clk dsi0pll_n2_div_clk = {
	.data = {		.data = {
	.max_div = 15,		.max_div = 15,
	@@ -136,6 +207,21 @@ static struct div_clk dsi0pll_n2_div_clk = {
	},		},
	};		};

			static struct div_clk dsi0pll_shadow_n2_div_clk = {
			.data = {
			.max_div = 15,
			.min_div = 1,
			},
			.ops = &shadow_n2_div_ops,
			.c = {
			.parent = &dsi0pll_shadow_post_n1_div_clk.c,
			.dbg_name = "dsi0pll_shadow_n2_div_clk",
			.ops = &shadow_n2_clk_src_ops,
			.flags = CLKFLAG_NO_RATE_CACHE,
			CLK_INIT(dsi0pll_shadow_n2_div_clk.c),
			},
			};

	static struct div_clk dsi1pll_n2_div_clk = {		static struct div_clk dsi1pll_n2_div_clk = {
	.data = {		.data = {
	.max_div = 15,		.max_div = 15,
	@@ -151,6 +237,21 @@ static struct div_clk dsi1pll_n2_div_clk = {
	},		},
	};		};

			static struct div_clk dsi1pll_shadow_n2_div_clk = {
			.data = {
			.max_div = 15,
			.min_div = 1,
			},
			.ops = &shadow_n2_div_ops,
			.c = {
			.parent = &dsi1pll_shadow_post_n1_div_clk.c,
			.dbg_name = "dsi1pll_shadow_n2_div_clk",
			.ops = &shadow_n2_clk_src_ops,
			.flags = CLKFLAG_NO_RATE_CACHE,
			CLK_INIT(dsi1pll_shadow_n2_div_clk.c),
			},
			};

	static struct div_clk dsi0pll_pixel_clk_src = {		static struct div_clk dsi0pll_pixel_clk_src = {
	.data = {		.data = {
	.div = 2,		.div = 2,
	@@ -159,13 +260,28 @@ static struct div_clk dsi0pll_pixel_clk_src = {
	},		},
	.c = {		.c = {
	.parent = &dsi0pll_n2_div_clk.c,		.parent = &dsi0pll_n2_div_clk.c,
	.dbg_name = "dsi0pll_pixel_clk_src_0",		.dbg_name = "dsi0pll_pixel_clk_src",
	.ops = &clk_ops_div,		.ops = &clk_ops_div,
	.flags = CLKFLAG_NO_RATE_CACHE,		.flags = CLKFLAG_NO_RATE_CACHE,
	CLK_INIT(dsi0pll_pixel_clk_src.c),		CLK_INIT(dsi0pll_pixel_clk_src.c),
	},		},
	};		};

			static struct div_clk dsi0pll_shadow_pixel_clk_src = {
			.data = {
			.div = 2,
			.min_div = 2,
			.max_div = 2,
			},
			.c = {
			.parent = &dsi0pll_shadow_n2_div_clk.c,
			.dbg_name = "dsi0pll_shadow_pixel_clk_src",
			.ops = &clk_ops_div,
			.flags = CLKFLAG_NO_RATE_CACHE,
			CLK_INIT(dsi0pll_shadow_pixel_clk_src.c),
			},
			};

	static struct div_clk dsi1pll_pixel_clk_src = {		static struct div_clk dsi1pll_pixel_clk_src = {
	.data = {		.data = {
	.div = 2,		.div = 2,
	@@ -181,30 +297,49 @@ static struct div_clk dsi1pll_pixel_clk_src = {
	},		},
	};		};

			static struct div_clk dsi1pll_shadow_pixel_clk_src = {
			.data = {
			.div = 2,
			.min_div = 2,
			.max_div = 2,
			},
			.c = {
			.parent = &dsi1pll_shadow_n2_div_clk.c,
			.dbg_name = "dsi1pll_shadow_pixel_clk_src",
			.ops = &clk_ops_div,
			.flags = CLKFLAG_NO_RATE_CACHE,
			CLK_INIT(dsi1pll_shadow_pixel_clk_src.c),
			},
			};

	static struct mux_clk dsi0pll_pixel_clk_mux = {		static struct mux_clk dsi0pll_pixel_clk_mux = {
	.num_parents = 1,		.num_parents = 2,
	.parents = (struct clk_src[]) {		.parents = (struct clk_src[]) {
	{&dsi0pll_pixel_clk_src.c, 0},		{&dsi0pll_pixel_clk_src.c, 0},
			{&dsi0pll_shadow_pixel_clk_src.c, 1},
	},		},
	.ops = &mdss_pixel_mux_ops,		.ops = &mdss_pixel_mux_ops,
	.c = {		.c = {
	.parent = &dsi0pll_pixel_clk_src.c,		.parent = &dsi0pll_pixel_clk_src.c,
	.dbg_name = "dsi0pll_pixel_clk_mux_0",		.dbg_name = "dsi0pll_pixel_clk_mux",
	.ops = &clk_ops_gen_mux,		.ops = &clk_ops_gen_mux_dsi,
			.flags = CLKFLAG_NO_RATE_CACHE,
	CLK_INIT(dsi0pll_pixel_clk_mux.c),		CLK_INIT(dsi0pll_pixel_clk_mux.c),
	}		}
	};		};

	static struct mux_clk dsi1pll_pixel_clk_mux = {		static struct mux_clk dsi1pll_pixel_clk_mux = {
	.num_parents = 1,		.num_parents = 2,
	.parents = (struct clk_src[]) {		.parents = (struct clk_src[]) {
	{&dsi1pll_pixel_clk_src.c, 0},		{&dsi1pll_pixel_clk_src.c, 0},
			{&dsi1pll_shadow_pixel_clk_src.c, 1},
	},		},
	.ops = &mdss_pixel_mux_ops,		.ops = &mdss_pixel_mux_ops,
	.c = {		.c = {
	.parent = &dsi1pll_pixel_clk_src.c,		.parent = &dsi1pll_pixel_clk_src.c,
	.dbg_name = "dsi1pll_pixel_clk_mux",		.dbg_name = "dsi1pll_pixel_clk_mux",
	.ops = &clk_ops_gen_mux,		.ops = &clk_ops_gen_mux_dsi,
			.flags = CLKFLAG_NO_RATE_CACHE,
	CLK_INIT(dsi1pll_pixel_clk_mux.c),		CLK_INIT(dsi1pll_pixel_clk_mux.c),
	}		}
	};		};
	@@ -223,6 +358,20 @@ static struct div_clk dsi0pll_byte_clk_src = {
	},		},
	};		};

			static struct div_clk dsi0pll_shadow_byte_clk_src = {
			.data = {
			.div = 8,
			.min_div = 8,
			.max_div = 8,
			},
			.c = {
			.parent = &dsi0pll_shadow_post_n1_div_clk.c,
			.dbg_name = "dsi0pll_shadow_byte_clk_src",
			.ops = &clk_ops_div,
			CLK_INIT(dsi0pll_shadow_byte_clk_src.c),
			},
			};

	static struct div_clk dsi1pll_byte_clk_src = {		static struct div_clk dsi1pll_byte_clk_src = {
	.data = {		.data = {
	.div = 8,		.div = 8,
	@@ -237,29 +386,47 @@ static struct div_clk dsi1pll_byte_clk_src = {
	},		},
	};		};

			static struct div_clk dsi1pll_shadow_byte_clk_src = {
			.data = {
			.div = 8,
			.min_div = 8,
			.max_div = 8,
			},
			.c = {
			.parent = &dsi1pll_shadow_post_n1_div_clk.c,
			.dbg_name = "dsi1pll_shadow_byte_clk_src",
			.ops = &clk_ops_div,
			CLK_INIT(dsi1pll_shadow_byte_clk_src.c),
			},
			};

	static struct mux_clk dsi0pll_byte_clk_mux = {		static struct mux_clk dsi0pll_byte_clk_mux = {
	.num_parents = 1,		.num_parents = 2,
	.parents = (struct clk_src[]) {		.parents = (struct clk_src[]) {
	{&dsi0pll_byte_clk_src.c, 0},		{&dsi0pll_byte_clk_src.c, 0},
			{&dsi0pll_shadow_byte_clk_src.c, 1},
	},		},
	.ops = &mdss_byte_mux_ops,		.ops = &mdss_byte_mux_ops,
	.c = {		.c = {
	.parent = &dsi0pll_byte_clk_src.c,		.parent = &dsi0pll_byte_clk_src.c,
	.dbg_name = "dsi0pll_byte_clk_mux",		.dbg_name = "dsi0pll_byte_clk_mux",
	.ops = &clk_ops_gen_mux_dsi,		.ops = &clk_ops_gen_mux_dsi,
			.flags = CLKFLAG_NO_RATE_CACHE,
	CLK_INIT(dsi0pll_byte_clk_mux.c),		CLK_INIT(dsi0pll_byte_clk_mux.c),
	}		}
	};		};
	static struct mux_clk dsi1pll_byte_clk_mux = {		static struct mux_clk dsi1pll_byte_clk_mux = {
	.num_parents = 1,		.num_parents = 2,
	.parents = (struct clk_src[]) {		.parents = (struct clk_src[]) {
	{&dsi1pll_byte_clk_src.c, 0},		{&dsi1pll_byte_clk_src.c, 0},
			{&dsi1pll_shadow_byte_clk_src.c, 1},
	},		},
	.ops = &mdss_byte_mux_ops,		.ops = &mdss_byte_mux_ops,
	.c = {		.c = {
	.parent = &dsi1pll_byte_clk_src.c,		.parent = &dsi1pll_byte_clk_src.c,
	.dbg_name = "dsi1pll_byte_clk_mux",		.dbg_name = "dsi1pll_byte_clk_mux",
	.ops = &clk_ops_gen_mux_dsi,		.ops = &clk_ops_gen_mux_dsi,
			.flags = CLKFLAG_NO_RATE_CACHE,
	CLK_INIT(dsi1pll_byte_clk_mux.c),		CLK_INIT(dsi1pll_byte_clk_mux.c),
	}		}
	};		};
	@@ -272,6 +439,11 @@ static struct clk_lookup mdss_dsi_pllcc_8996[] = {
	CLK_LIST(dsi0pll_n2_div_clk),		CLK_LIST(dsi0pll_n2_div_clk),
	CLK_LIST(dsi0pll_post_n1_div_clk),		CLK_LIST(dsi0pll_post_n1_div_clk),
	CLK_LIST(dsi0pll_vco_clk),		CLK_LIST(dsi0pll_vco_clk),
			CLK_LIST(dsi0pll_shadow_byte_clk_src),
			CLK_LIST(dsi0pll_shadow_pixel_clk_src),
			CLK_LIST(dsi0pll_shadow_n2_div_clk),
			CLK_LIST(dsi0pll_shadow_post_n1_div_clk),
			CLK_LIST(dsi0pll_shadow_vco_clk),
	};		};

	static struct clk_lookup mdss_dsi_pllcc_8996_1[] = {		static struct clk_lookup mdss_dsi_pllcc_8996_1[] = {
	@@ -282,6 +454,11 @@ static struct clk_lookup mdss_dsi_pllcc_8996_1[] = {
	CLK_LIST(dsi1pll_n2_div_clk),		CLK_LIST(dsi1pll_n2_div_clk),
	CLK_LIST(dsi1pll_post_n1_div_clk),		CLK_LIST(dsi1pll_post_n1_div_clk),
	CLK_LIST(dsi1pll_vco_clk),		CLK_LIST(dsi1pll_vco_clk),
			CLK_LIST(dsi1pll_shadow_byte_clk_src),
			CLK_LIST(dsi1pll_shadow_pixel_clk_src),
			CLK_LIST(dsi1pll_shadow_n2_div_clk),
			CLK_LIST(dsi1pll_shadow_post_n1_div_clk),
			CLK_LIST(dsi1pll_shadow_vco_clk),
	};		};

	int dsi_pll_clock_register_8996(struct platform_device *pdev,		int dsi_pll_clock_register_8996(struct platform_device *pdev,
	@@ -319,10 +496,14 @@ int dsi_pll_clock_register_8996(struct platform_device *pdev,
	n2_clk_src_ops = clk_ops_slave_div;		n2_clk_src_ops = clk_ops_slave_div;
	n2_clk_src_ops.prepare = dsi_pll_div_prepare;		n2_clk_src_ops.prepare = dsi_pll_div_prepare;

			shadow_n2_clk_src_ops = clk_ops_slave_div;

	/* hr_ockl2, byte, vco pll */		/* hr_ockl2, byte, vco pll */
	post_n1_div_clk_src_ops = clk_ops_div;		post_n1_div_clk_src_ops = clk_ops_div;
	post_n1_div_clk_src_ops.prepare = dsi_pll_div_prepare;		post_n1_div_clk_src_ops.prepare = dsi_pll_div_prepare;

			shadow_post_n1_div_clk_src_ops = clk_ops_div;

	byte_clk_src_ops = clk_ops_div;		byte_clk_src_ops = clk_ops_div;
	byte_clk_src_ops.prepare = dsi_pll_div_prepare;		byte_clk_src_ops.prepare = dsi_pll_div_prepare;

	@@ -338,6 +519,12 @@ int dsi_pll_clock_register_8996(struct platform_device *pdev,
	dsi1pll_n2_div_clk.priv = pll_res;		dsi1pll_n2_div_clk.priv = pll_res;
	dsi1pll_vco_clk.priv = pll_res;		dsi1pll_vco_clk.priv = pll_res;

			dsi1pll_shadow_byte_clk_src.priv = pll_res;
			dsi1pll_shadow_pixel_clk_src.priv = pll_res;
			dsi1pll_shadow_post_n1_div_clk.priv = pll_res;
			dsi1pll_shadow_n2_div_clk.priv = pll_res;
			dsi1pll_shadow_vco_clk.priv = pll_res;

	pll_res->vco_delay = VCO_DELAY_USEC;		pll_res->vco_delay = VCO_DELAY_USEC;
	rc = of_msm_clock_register(pdev->dev.of_node,		rc = of_msm_clock_register(pdev->dev.of_node,
	mdss_dsi_pllcc_8996_1,		mdss_dsi_pllcc_8996_1,
	@@ -349,6 +536,12 @@ int dsi_pll_clock_register_8996(struct platform_device *pdev,
	dsi0pll_n2_div_clk.priv = pll_res;		dsi0pll_n2_div_clk.priv = pll_res;
	dsi0pll_vco_clk.priv = pll_res;		dsi0pll_vco_clk.priv = pll_res;

			dsi0pll_shadow_byte_clk_src.priv = pll_res;
			dsi0pll_shadow_pixel_clk_src.priv = pll_res;
			dsi0pll_shadow_post_n1_div_clk.priv = pll_res;
			dsi0pll_shadow_n2_div_clk.priv = pll_res;
			dsi0pll_shadow_vco_clk.priv = pll_res;

	pll_res->vco_delay = VCO_DELAY_USEC;		pll_res->vco_delay = VCO_DELAY_USEC;
	rc = of_msm_clock_register(pdev->dev.of_node,		rc = of_msm_clock_register(pdev->dev.of_node,
	mdss_dsi_pllcc_8996,		mdss_dsi_pllcc_8996,

drivers/clk/qcom/mdss/mdss-dsi-pll-8996.h

+25 −2

Original line number	Original line	Diff line number	Diff line
	@@ -38,11 +38,12 @@
	#define DSIPHY_PLL_RESETSM_CNTRL5 0x043c		#define DSIPHY_PLL_RESETSM_CNTRL5 0x043c
	#define DSIPHY_PLL_KVCO_DIV_REF1 0x0440		#define DSIPHY_PLL_KVCO_DIV_REF1 0x0440
	#define DSIPHY_PLL_KVCO_DIV_REF2 0x0444		#define DSIPHY_PLL_KVCO_DIV_REF2 0x0444

	#define DSIPHY_PLL_KVCO_COUNT1 0x0448		#define DSIPHY_PLL_KVCO_COUNT1 0x0448
	#define DSIPHY_PLL_KVCO_COUNT2 0x044c		#define DSIPHY_PLL_KVCO_COUNT2 0x044c
	#define DSIPHY_PLL_VREF_CFG1 0x045c		#define DSIPHY_PLL_VREF_CFG1 0x045c

			#define DSIPHY_PLL_KVCO_CODE 0x0458

	#define DSIPHY_PLL_VCO_DIV_REF1 0x046c		#define DSIPHY_PLL_VCO_DIV_REF1 0x046c
	#define DSIPHY_PLL_VCO_DIV_REF2 0x0470		#define DSIPHY_PLL_VCO_DIV_REF2 0x0470
	#define DSIPHY_PLL_VCO_COUNT1 0x0474		#define DSIPHY_PLL_VCO_COUNT1 0x0474
	@@ -51,7 +52,7 @@
	#define DSIPHY_PLL_PLLLOCK_CMP2 0x0480		#define DSIPHY_PLL_PLLLOCK_CMP2 0x0480
	#define DSIPHY_PLL_PLLLOCK_CMP3 0x0484		#define DSIPHY_PLL_PLLLOCK_CMP3 0x0484
	#define DSIPHY_PLL_PLLLOCK_CMP_EN 0x0488		#define DSIPHY_PLL_PLLLOCK_CMP_EN 0x0488
			#define DSIPHY_PLL_PLL_VCO_TUNE 0x048C
	#define DSIPHY_PLL_DEC_START 0x0490		#define DSIPHY_PLL_DEC_START 0x0490
	#define DSIPHY_PLL_SSC_EN_CENTER 0x0494		#define DSIPHY_PLL_SSC_EN_CENTER 0x0494
	#define DSIPHY_PLL_SSC_ADJ_PER1 0x0498		#define DSIPHY_PLL_SSC_ADJ_PER1 0x0498
	@@ -76,6 +77,22 @@
	#define DSIPHY_PLL_PLL_ICP_SET 0x04fc		#define DSIPHY_PLL_PLL_ICP_SET 0x04fc
	#define DSIPHY_PLL_PLL_LPF1 0x0500		#define DSIPHY_PLL_PLL_LPF1 0x0500
	#define DSIPHY_PLL_PLL_LPF2_POSTDIV 0x0504		#define DSIPHY_PLL_PLL_LPF2_POSTDIV 0x0504
			#define DSIPHY_PLL_PLL_BANDGAP 0x0508

			#define DSI_DYNAMIC_REFRESH_PLL_CTRL15 0x050
			#define DSI_DYNAMIC_REFRESH_PLL_CTRL19 0x060
			#define DSI_DYNAMIC_REFRESH_PLL_CTRL20 0x064
			#define DSI_DYNAMIC_REFRESH_PLL_CTRL21 0x068
			#define DSI_DYNAMIC_REFRESH_PLL_CTRL22 0x06C
			#define DSI_DYNAMIC_REFRESH_PLL_CTRL23 0x070
			#define DSI_DYNAMIC_REFRESH_PLL_CTRL24 0x074
			#define DSI_DYNAMIC_REFRESH_PLL_CTRL25 0x078
			#define DSI_DYNAMIC_REFRESH_PLL_CTRL26 0x07C
			#define DSI_DYNAMIC_REFRESH_PLL_CTRL27 0x080
			#define DSI_DYNAMIC_REFRESH_PLL_CTRL28 0x084
			#define DSI_DYNAMIC_REFRESH_PLL_CTRL29 0x088
			#define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR 0x094
			#define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2 0x098

	struct dsi_pll_input {		struct dsi_pll_input {
	u32 fref; /* 19.2 Mhz, reference clk */		u32 fref; /* 19.2 Mhz, reference clk */
	@@ -183,6 +200,12 @@ enum {
	int pll_vco_set_rate_8996(struct clk *c, unsigned long rate);		int pll_vco_set_rate_8996(struct clk *c, unsigned long rate);
	long pll_vco_round_rate_8996(struct clk *c, unsigned long rate);		long pll_vco_round_rate_8996(struct clk *c, unsigned long rate);
	enum handoff pll_vco_handoff_8996(struct clk *c);		enum handoff pll_vco_handoff_8996(struct clk *c);
			enum handoff shadow_pll_vco_handoff_8996(struct clk *c);
			int shadow_post_n1_div_set_div(struct div_clk *clk, int div);
			int shadow_post_n1_div_get_div(struct div_clk *clk);
			int shadow_n2_div_set_div(struct div_clk *clk, int div);
			int shadow_n2_div_get_div(struct div_clk *clk);
			int shadow_pll_vco_set_rate_8996(struct clk *c, unsigned long rate);
	int pll_vco_prepare_8996(struct clk *c);		int pll_vco_prepare_8996(struct clk *c);
	void pll_vco_unprepare_8996(struct clk *c);		void pll_vco_unprepare_8996(struct clk *c);
	int set_mdss_byte_mux_sel_8996(struct mux_clk *clk, int sel);		int set_mdss_byte_mux_sel_8996(struct mux_clk *clk, int sel);

drivers/clk/qcom/mdss/mdss-pll.h

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -21,7 +21,8 @@
	#define MDSS_PLL_REG_R(base, offset) readl_relaxed((base) + (offset))		#define MDSS_PLL_REG_R(base, offset) readl_relaxed((base) + (offset))

	#define PLL_CALC_DATA(addr0, addr1, data0, data1) \		#define PLL_CALC_DATA(addr0, addr1, data0, data1) \
	(((data1) << 24) \| (((addr1)/4) << 16) \| ((data0) << 8) \| ((addr0)/4))		(((data1) << 24) \| ((((addr1) / 4) & 0xFF) << 16) \| \
			((data0) << 8) \| (((addr0) / 4) & 0xFF))

	#define MDSS_DYN_PLL_REG_W(base, offset, addr0, addr1, data0, data1) \		#define MDSS_DYN_PLL_REG_W(base, offset, addr0, addr1, data0, data1) \
	writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \		writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \