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Commit eb1d7eae authored by Ulf Hansson's avatar Ulf Hansson Committed by Mike Turquette
Browse files

clk: ux500: Register ssp clock lookups for u8500 



Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Acked-by: default avatarLee Jones <lee.jones@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 1c73491a

drivers/clk/ux500/u8500_clk.c

+6 −0
Original line number Diff line number Diff line
@@ -324,8 +324,11 @@ void u8500_clk_init(void) 


	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,

				BIT(1), 0);

	clk_register_clkdev(clk, "apb_pclk", "ssp0");



	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE,

				BIT(2), 0);

	clk_register_clkdev(clk, "apb_pclk", "ssp1");



	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE,

				BIT(3), 0);
@@ -468,8 +471,11 @@ void u8500_clk_init(void) 
	/* Periph3 */

	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",

			U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "ssp0");



	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",

			U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "ssp1");



	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",

			U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE);