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Commit eaecf032 authored by Alexandre Courbot's avatar Alexandre Courbot Committed by Ben Skeggs
Browse files

make RAM device optional 



Having a RAM device does not make sense for chips like GK20A which have
no dedicated video memory. The dummy RAM device that we used so far
works as a temporary band-aid, but in the longer term it is desirable
for the driver to be able to work without any kind of VRAM.

This patch adds a few conditionals in places where a RAM device was
assumed to be present and allows some more objects to be allocated from
the TT domain, allowing Nouveau to handle GPUs for which
pfb->ram == NULL.

Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent c6a7b026

drivers/gpu/drm/nouveau/nouveau_display.c

+8 −1
Original line number Diff line number Diff line
@@ -869,13 +869,20 @@ nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev, 
			    struct drm_mode_create_dumb *args)

{

	struct nouveau_bo *bo;

	uint32_t domain;

	int ret;



	args->pitch = roundup(args->width * (args->bpp / 8), 256);

	args->size = args->pitch * args->height;

	args->size = roundup(args->size, PAGE_SIZE);



	ret = nouveau_gem_new(dev, args->size, 0, NOUVEAU_GEM_DOMAIN_VRAM, 0, 0, &bo);

	/* Use VRAM if there is any ; otherwise fallback to system memory */

	if (nouveau_drm(dev)->device.info.ram_size != 0)

		domain = NOUVEAU_GEM_DOMAIN_VRAM;

	else

		domain = NOUVEAU_GEM_DOMAIN_GART;



	ret = nouveau_gem_new(dev, args->size, 0, domain, 0, 0, &bo);

	if (ret)

		return ret;

drivers/gpu/drm/nouveau/nouveau_ttm.c

+3 −0
Original line number Diff line number Diff line
@@ -82,6 +82,9 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, 
	u32 size_nc = 0;

	int ret;



	if (drm->device.info.ram_size == 0)

		return -ENOMEM;



	if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)

		size_nc = 1 << nvbo->page_shift;

drivers/gpu/drm/nouveau/nv84_fence.c

+11 −3
Original line number Diff line number Diff line
@@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) 
{

	struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device);

	struct nv84_fence_priv *priv;

	u32 domain;

	int ret;



	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
@@ -231,10 +232,17 @@ nv84_fence_create(struct nouveau_drm *drm) 
	priv->base.context_base = fence_context_alloc(priv->base.contexts);

	priv->base.uevent = true;



	ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0,

			     TTM_PL_FLAG_VRAM, 0, 0, NULL, NULL, &priv->bo);

	/* Use VRAM if there is any ; otherwise fallback to system memory */

	domain = drm->device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :

			 /*

			  * fences created in sysmem must be non-cached or we

			  * will lose CPU/GPU coherency!

			  */

			 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;

	ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, domain, 0,

			     0, NULL, NULL, &priv->bo);

	if (ret == 0) {

		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false);

		ret = nouveau_bo_pin(priv->bo, domain, false);

		if (ret == 0) {

			ret = nouveau_bo_map(priv->bo);

			if (ret)

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+7 −3
Original line number Diff line number Diff line
@@ -139,9 +139,13 @@ nvkm_devobj_info(struct nvkm_object *object, void *data, u32 size) 


	args->v0.chipset  = device->chipset;

	args->v0.revision = device->chiprev;

	if (pfb)  args->v0.ram_size = args->v0.ram_user = pfb->ram->size;

	else      args->v0.ram_size = args->v0.ram_user = 0;

	if (imem) args->v0.ram_user = args->v0.ram_user - imem->reserved;

	if (pfb && pfb->ram)

		args->v0.ram_size = args->v0.ram_user = pfb->ram->size;

	else

		args->v0.ram_size = args->v0.ram_user = 0;

	if (imem && args->v0.ram_size > 0)

		args->v0.ram_user = args->v0.ram_user - imem->reserved;



	return 0;

}

drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c

+1 −1
Original line number Diff line number Diff line
@@ -184,7 +184,7 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) 
	nv_debug(clk, "setting performance state %d\n", pstatei);

	clk->pstate = pstatei;



	if (pfb->ram->calc) {

	if (pfb->ram && pfb->ram->calc) {

		int khz = pstate->base.domain[nv_clk_src_mem];

		do {

			ret = pfb->ram->calc(pfb, khz);