Merge "drm/msm/dsi-staging: toggle resync fifo after clock on" (ea8b6f70) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -215,6 +215,7 @@ static void dsi_catalog_phy_3_0_init(struct dsi_phy_hw *phy)
		dsi_phy_hw_v3_0_is_lanes_in_ulps;
		phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v3_0;
		phy->ops.phy_lane_reset = dsi_phy_hw_v3_0_lane_reset;
		phy->ops.toggle_resync_fifo = dsi_phy_hw_v3_0_toggle_resync_fifo;
		}

		/**

+1 −0

Original line number	Diff line number	Diff line
		@@ -103,6 +103,7 @@ bool dsi_phy_hw_v3_0_is_lanes_in_ulps(u32 lanes, u32 ulps_lanes);
		int dsi_phy_hw_timing_val_v3_0(struct dsi_phy_per_lane_cfgs *timing_cfg,
		u32 *timing_val, u32 size);
		int dsi_phy_hw_v3_0_lane_reset(struct dsi_phy_hw *phy);
		void dsi_phy_hw_v3_0_toggle_resync_fifo(struct dsi_phy_hw *phy);

		/* DSI controller common ops */
		u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);

+23 −0

Original line number	Diff line number	Diff line
		@@ -2164,6 +2164,20 @@ static int dsi_display_phy_reset_config(struct dsi_display *display,
		return 0;
		}

		static void dsi_display_toggle_resync_fifo(struct dsi_display *display)
		{
		struct dsi_display_ctrl *ctrl;
		int i;

		if (!display)
		return;

		for (i = 0; i < display->ctrl_count; i++) {
		ctrl = &display->ctrl[i];
		dsi_phy_toggle_resync_fifo(ctrl->phy);
		}
		}

		static int dsi_display_ctrl_update(struct dsi_display *display)
		{
		int rc = 0;
		@@ -3089,6 +3103,15 @@ int dsi_post_clkon_cb(void *priv,
		dsi_display_ctrl_irq_update(display, true);
		}
		if (clk & DSI_LINK_CLK) {
		/*
		* Toggle the resync FIFO everytime clock changes, except
		* when cont-splash screen transition is going on.
		* Toggling resync FIFO during cont splash transition
		* can lead to blinks on the display.
		*/
		if (!display->is_cont_splash_enabled)
		dsi_display_toggle_resync_fifo(display);

		if (display->ulps_enabled) {
		rc = dsi_display_set_ulps(display, false);
		if (rc) {

+10 −0

Original line number	Diff line number	Diff line
		@@ -752,6 +752,16 @@ static int dsi_phy_disable_ulps(struct msm_dsi_phy *phy,
		return 0;
		}

		void dsi_phy_toggle_resync_fifo(struct msm_dsi_phy *phy)
		{
		if (!phy)
		return;

		if (!phy->hw.ops.toggle_resync_fifo)
		return;

		phy->hw.ops.toggle_resync_fifo(&phy->hw);
		}

		int dsi_phy_set_ulps(struct msm_dsi_phy phy, struct dsi_host_config config,
		bool enable, bool clamp_enabled)

+11 −1

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
		* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -249,6 +249,16 @@ int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
		*/
		int dsi_phy_lane_reset(struct msm_dsi_phy *phy);

		/**
		* dsi_phy_toggle_resync_fifo() - toggle resync retime FIFO
		* @phy: DSI PHY handle
		*
		* Toggle the resync retime FIFO to synchronize the data paths.
		* This should be done everytime there is a change in the link clock
		* rate
		*/
		void dsi_phy_toggle_resync_fifo(struct msm_dsi_phy *phy);

		/**
		* dsi_phy_drv_register() - register platform driver for dsi phy
		*/