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Commit ea4f1cc2 authored by Odelu Kukatla's avatar Odelu Kukatla
Browse files

clk: qcom: Update the frequency level for mdss_mdp_clk for smd670 



286.67MHz frequency level of disp_cc_mdss_mdp_clk clock requires
to be changed to 286.666667MHz on sdm670, so update the same.

Change-Id: I0692bf5e14612c4f95667e8c1357971d885ee367
Signed-off-by: default avatarOdelu Kukatla <okukatla@codeaurora.org>
parent 5c1f0d88

drivers/clk/qcom/dispcc-sdm845.c

+1 −1
Original line number Diff line number Diff line
@@ -390,7 +390,7 @@ static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sdm670[] = { 
	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),

	F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),

	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),

	F(286670000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),

	F(286666667, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),

	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),

	F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),

	F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),