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Commit ea426e6c authored by Mike Frysinger's avatar Mike Frysinger
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Blackfin: unify cache init functions 



The CPLB implementations (mpu/nompu) had exact copies of the cacheinit
code.  Even the i/d cache functions are largely the same.  So unify them
both in the common kernel cache code.

Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent e78feaae

arch/blackfin/kernel/cplb-mpu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
# arch/blackfin/kernel/cplb-nompu/Makefile

#



obj-y := cplbinit.o cacheinit.o cplbmgr.o

obj-y := cplbinit.o cplbmgr.o



CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \

		    -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \

arch/blackfin/kernel/cplb-mpu/cacheinit.c

deleted100644 → 0
+0 −71
Original line number Diff line number Diff line 
/*

 *               Copyright 2004-2007 Analog Devices Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, see the file COPYING, or write

 * to the Free Software Foundation, Inc.,

 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

 */



#include <linux/cpu.h>



#include <asm/cacheflush.h>

#include <asm/blackfin.h>

#include <asm/cplb.h>

#include <asm/cplbinit.h>



#if defined(CONFIG_BFIN_ICACHE)

void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)

{

	unsigned long ctrl;

	int i;



	for (i = 0; i < MAX_CPLBS; i++) {

		bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);

		bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);

	}

	ctrl = bfin_read_IMEM_CONTROL();

	ctrl |= IMC | ENICPLB;

	/* CSYNC to ensure load store ordering */

	CSYNC();

	bfin_write_IMEM_CONTROL(ctrl);

	SSYNC();

}

#endif



#if defined(CONFIG_BFIN_DCACHE)

void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)

{

	unsigned long ctrl;

	int i;



	for (i = 0; i < MAX_CPLBS; i++) {

		bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);

		bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);

	}



	ctrl = bfin_read_DMEM_CONTROL();



	/*

	 *  Anomaly notes:

	 *  05000287 - We implement workaround #2 - Change the DMEM_CONTROL

	 *  register, so that the port preferences for DAG0 and DAG1 are set

	 *  to port B

	 */

	ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);

	/* CSYNC to ensure load store ordering */

	CSYNC();

	bfin_write_DMEM_CONTROL(ctrl);

	SSYNC();

}

#endif

arch/blackfin/kernel/cplb-nompu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
# arch/blackfin/kernel/cplb-nompu/Makefile

#



obj-y := cplbinit.o cacheinit.o cplbmgr.o

obj-y := cplbinit.o cplbmgr.o



CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \

		    -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \

arch/blackfin/kernel/cplb-nompu/cacheinit.c

deleted100644 → 0
+0 −71
Original line number Diff line number Diff line 
/*

 *               Copyright 2004-2007 Analog Devices Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, see the file COPYING, or write

 * to the Free Software Foundation, Inc.,

 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

 */



#include <linux/cpu.h>



#include <asm/cacheflush.h>

#include <asm/blackfin.h>

#include <asm/cplb.h>

#include <asm/cplbinit.h>



#if defined(CONFIG_BFIN_ICACHE)

void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)

{

	unsigned long ctrl;

	int i;



	for (i = 0; i < MAX_CPLBS; i++) {

		bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);

		bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);

	}

	ctrl = bfin_read_IMEM_CONTROL();

	ctrl |= IMC | ENICPLB;

	/* CSYNC to ensure load store ordering */

	CSYNC();

	bfin_write_IMEM_CONTROL(ctrl);

	SSYNC();

}

#endif



#if defined(CONFIG_BFIN_DCACHE)

void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)

{

	unsigned long ctrl;

	int i;



	for (i = 0; i < MAX_CPLBS; i++) {

		bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);

		bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);

	}



	ctrl = bfin_read_DMEM_CONTROL();



	/*

	 *  Anomaly notes:

	 *  05000287 - We implement workaround #2 - Change the DMEM_CONTROL

	 *  register, so that the port preferences for DAG0 and DAG1 are set

	 *  to port B

	 */

	ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);

	/* CSYNC to ensure load store ordering */

	CSYNC();

	bfin_write_DMEM_CONTROL(ctrl);

	SSYNC();

}

#endif

arch/blackfin/mach-common/cache-c.c

+43 −1
Original line number Diff line number Diff line 
/*

 * Blackfin cache control code (simpler control-style functions)

 *

 * Copyright 2004-2008 Analog Devices Inc.

 * Copyright 2004-2009 Analog Devices Inc.

 *

 * Enter bugs at http://blackfin.uclinux.org/

 *

 * Licensed under the GPL-2 or later.

 */



#include <linux/init.h>

#include <asm/blackfin.h>

#include <asm/cplbinit.h>



/* Invalidate the Entire Data cache by

 * clearing DMC[1:0] bits
@@ -34,3 +36,43 @@ void blackfin_invalidate_entire_icache(void) 
	SSYNC();

}



#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)



static void

bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,

                unsigned long cplb_data, unsigned long mem_control,

                unsigned long mem_mask)

{

	int i;



	for (i = 0; i < MAX_CPLBS; i++) {

		bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);

		bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);

	}



	_enable_cplb(mem_control, mem_mask);

}



#ifdef CONFIG_BFIN_ICACHE

void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)

{

	bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,

		(IMC | ENICPLB));

}

#endif



#ifdef CONFIG_BFIN_DCACHE

void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)

{

	/*

	 *  Anomaly notes:

	 *  05000287 - We implement workaround #2 - Change the DMEM_CONTROL

	 *  register, so that the port preferences for DAG0 and DAG1 are set

	 *  to port B

	 */

	bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,

		(DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));

}

#endif



#endif