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Commit e9fe51c6 authored by Shobhit Kumar's avatar Shobhit Kumar Committed by Daniel Vetter
Browse files

drm/i915: Use FLISDSI interface for band gap reset 



v2: Rebased on latest code

Signed-off-by: default avatarShobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: default avatarYogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Reviewed-by: default avatarJani <Nikula&lt;jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b9f5e07d

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -2475,6 +2475,8 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 
		   enum intel_sbi_destination destination);

void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,

		     enum intel_sbi_destination destination);

u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);

void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);



int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);

int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -362,6 +362,7 @@ 
#define   IOSF_PORT_CCK				0x14

#define   IOSF_PORT_CCU				0xA9

#define   IOSF_PORT_GPS_CORE			0x48

#define   IOSF_PORT_FLISDSI			0x1B

#define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)

#define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)

drivers/gpu/drm/i915/intel_dsi.c

+8 −39
Original line number Diff line number Diff line
@@ -37,49 +37,18 @@ 
static const struct intel_dsi_device intel_dsi_devices[] = {

};





static void vlv_cck_modify(struct drm_i915_private *dev_priv, u32 reg, u32 val,

			   u32 mask)

{

	u32 tmp = vlv_cck_read(dev_priv, reg);

	tmp &= ~mask;

	tmp |= val;

	vlv_cck_write(dev_priv, reg, tmp);

}



static void band_gap_wa(struct drm_i915_private *dev_priv)

static void band_gap_reset(struct drm_i915_private *dev_priv)

{

	mutex_lock(&dev_priv->dpio_lock);



	/* Enable bandgap fix in GOP driver */

	vlv_cck_modify(dev_priv, 0x6D, 0x00010000, 0x00030000);

	msleep(20);

	vlv_cck_modify(dev_priv, 0x6E, 0x00010000, 0x00030000);

	msleep(20);

	vlv_cck_modify(dev_priv, 0x6F, 0x00010000, 0x00030000);

	msleep(20);

	vlv_cck_modify(dev_priv, 0x00, 0x00008000, 0x00008000);

	msleep(20);

	vlv_cck_modify(dev_priv, 0x00, 0x00000000, 0x00008000);

	msleep(20);



	/* Turn Display Trunk on */

	vlv_cck_modify(dev_priv, 0x6B, 0x00020000, 0x00030000);

	msleep(20);



	vlv_cck_modify(dev_priv, 0x6C, 0x00020000, 0x00030000);

	msleep(20);



	vlv_cck_modify(dev_priv, 0x6D, 0x00020000, 0x00030000);

	msleep(20);

	vlv_cck_modify(dev_priv, 0x6E, 0x00020000, 0x00030000);

	msleep(20);

	vlv_cck_modify(dev_priv, 0x6F, 0x00020000, 0x00030000);

	vlv_flisdsi_write(dev_priv, 0x08, 0x0001);

	vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);

	vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);

	udelay(150);

	vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);

	vlv_flisdsi_write(dev_priv, 0x08, 0x0000);



	mutex_unlock(&dev_priv->dpio_lock);



	/* Need huge delay, otherwise clock is not stable */

	msleep(100);

}



static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
@@ -364,7 +333,7 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder) 
	vlv_enable_dsi_pll(intel_encoder);



	/* XXX: Location of the call */

	band_gap_wa(dev_priv);

	band_gap_reset(dev_priv);



	/* escape clock divider, 20MHz, shared for A and C. device ready must be

	 * off when doing this! txclkesc? */

drivers/gpu/drm/i915/intel_sideband.c

+14 −0
Original line number Diff line number Diff line
@@ -249,3 +249,17 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 
		return;

	}

}



u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)

{

	u32 val = 0;

	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,

					DPIO_OPCODE_REG_READ, reg, &val);

	return val;

}



void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

{

	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,

					DPIO_OPCODE_REG_WRITE, reg, &val);

}