Commit e9de1fd8 authored Feb 16, 2017 by Mayank Rana

ARM: dts: msm: Use correct ahb2phy_top_cfg register address on SDM845



Currently used ahb2phy_top_cfg register address with USB dwc3 device
node is not proper. This used register address is not accessible by
APPS. Hence use correct address to configure USB PHY read/write wait
states.

Change-Id: I76ade10cf3781aa5e28b12d659010a1079134aeb
Signed-off-by: Mayank Rana <mrana@codeaurora.org>

parent 3479e4d0

arch/arm64/boot/dts/qcom/sdm845-usb.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -16,7 +16,7 @@
		usb3: ssusb@a600000 {
		compatible = "qcom,dwc-usb3-msm";
		reg = <0x0a600000 0xf8c00>,
		<0x0141e000 0x400>;
		<0x088ee000 0x400>;
		reg-names = "core_base", "ahb2phy_base";
		#address-cells = <1>;
		#size-cells = <1>;