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Commit e927ecde authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Disable SF pipelined attribute fetch for SNB 



According to Bspec we need to disable SF pipelined attribute fetch
whenever SF outputs exceed 16 and normal clip mode is used. A quick
glance at Mesa suggests that these conditions could happen. So let's
just always set the magic bit.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarKenneth Graunke <kenneth@whitecape.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b8a5ff8d

drivers/gpu/drm/i915/i915_reg.h

+2 −1
Original line number Diff line number Diff line
@@ -789,7 +789,8 @@ 
#define _3D_CHICKEN3	0x02090

#define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)

#define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)

#define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x)<<1)

#define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x)<<1) /* gen8+ */

#define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */



#define MI_MODE		0x0209c

# define VS_TIMER_DISPATCH				(1 << 6)

drivers/gpu/drm/i915/intel_pm.c

+8 −0
Original line number Diff line number Diff line
@@ -4697,6 +4697,14 @@ static void gen6_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |

		   _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);



	/*

	 * Bspec says:

	 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and

	 * 3DSTATE_SF number of SF output attributes is more than 16."

	 */

	I915_WRITE(_3D_CHICKEN3,

		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));



	/*

	 * According to the spec the following bits should be

	 * set in order to enable memory self-refresh and fbc: