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Commit e90d016f authored by Dhaval Patel's avatar Dhaval Patel
Browse files

drm/msm/sde: increase wait time for ctl_start irq 



It may possible that sde driver triggers the frame
on read_ptr boundary. That may miss the current vsync
cycle kickoff window and frame is picked up on next
vsync_cycle. This may cause to generate the ctl_start
at 2 vsync boundary and fail the ctl_start wait. A 4
vsync wait increase allows remove such false alarm
from ctl_start error

Change-Id: I1051c4dc443f338a3cf158815d3db9cc52d6db3c
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent f5d98565

drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c

+1 −4
Original line number Diff line number Diff line
@@ -34,9 +34,6 @@ 


#define PP_TIMEOUT_MAX_TRIALS	10



/* wait for 2 vyncs only */

#define CTL_START_TIMEOUT_MS	32



/*

 * Tearcheck sync start and continue thresholds are empirically found

 * based on common panels In the future, may want to allow panels to override
@@ -1007,7 +1004,7 @@ static int _sde_encoder_phys_cmd_wait_for_ctl_start( 


	wait_info.wq = &phys_enc->pending_kickoff_wq;

	wait_info.atomic_cnt = &phys_enc->pending_ctlstart_cnt;

	wait_info.timeout_ms = CTL_START_TIMEOUT_MS;

	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;



	/* slave encoder doesn't enable for ppsplit */

	if (_sde_encoder_phys_is_ppsplit_slave(phys_enc))