Merge "msm: kgsl: Correctly derive RAM cycles from GBIF perf counters" (e7ab2d20) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/msm/a6xx_reg.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -764,6 +764,12 @@
		#define A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x3119
		#define A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x311a

		/* GBIF countables */
		#define GBIF_AXI0_READ_DATA_TOTAL_BEATS 34
		#define GBIF_AXI1_READ_DATA_TOTAL_BEATS 35
		#define GBIF_AXI0_WRITE_DATA_TOTAL_BEATS 46
		#define GBIF_AXI1_WRITE_DATA_TOTAL_BEATS 47

		/* GBIF registers */
		#define A6XX_GBIF_HALT 0x3c45
		#define A6XX_GBIF_HALT_ACK 0x3c46

drivers/gpu/msm/adreno.c

+104 −21

Original line number	Diff line number	Diff line
		@@ -37,6 +37,7 @@
		#include "adreno_trace.h"

		#include "a3xx_reg.h"
		#include "a6xx_reg.h"
		#include "adreno_snapshot.h"

		/* Include the master list of GPU cores that are supported */
		@@ -1639,8 +1640,66 @@ static int _adreno_start(struct adreno_device *adreno_dev)
		adreno_dev->starved_ram_lo_ch1 = 0;
		}
		}

		if (adreno_dev->ram_cycles_lo == 0) {
		ret = adreno_perfcounter_get(adreno_dev,
		KGSL_PERFCOUNTER_GROUP_VBIF,
		GBIF_AXI0_READ_DATA_TOTAL_BEATS,
		&adreno_dev->ram_cycles_lo, NULL,
		PERFCOUNTER_FLAG_KERNEL);

		if (ret) {
		KGSL_DRV_ERR(device,
		"Unable to get perf counters for bus DCVS\n");
		adreno_dev->ram_cycles_lo = 0;
		}
		}

		if (adreno_dev->ram_cycles_lo_ch1_read == 0) {
		ret = adreno_perfcounter_get(adreno_dev,
		KGSL_PERFCOUNTER_GROUP_VBIF,
		GBIF_AXI1_READ_DATA_TOTAL_BEATS,
		&adreno_dev->ram_cycles_lo_ch1_read,
		NULL,
		PERFCOUNTER_FLAG_KERNEL);

		if (ret) {
		KGSL_DRV_ERR(device,
		"Unable to get perf counters for bus DCVS\n");
		adreno_dev->ram_cycles_lo_ch1_read = 0;
		}
		}

		if (adreno_dev->ram_cycles_lo_ch0_write == 0) {
		ret = adreno_perfcounter_get(adreno_dev,
		KGSL_PERFCOUNTER_GROUP_VBIF,
		GBIF_AXI0_WRITE_DATA_TOTAL_BEATS,
		&adreno_dev->ram_cycles_lo_ch0_write,
		NULL,
		PERFCOUNTER_FLAG_KERNEL);

		if (ret) {
		KGSL_DRV_ERR(device,
		"Unable to get perf counters for bus DCVS\n");
		adreno_dev->ram_cycles_lo_ch0_write = 0;
		}
		}

		if (adreno_dev->ram_cycles_lo_ch1_write == 0) {
		ret = adreno_perfcounter_get(adreno_dev,
		KGSL_PERFCOUNTER_GROUP_VBIF,
		GBIF_AXI1_WRITE_DATA_TOTAL_BEATS,
		&adreno_dev->ram_cycles_lo_ch1_write,
		NULL,
		PERFCOUNTER_FLAG_KERNEL);

		if (ret) {
		KGSL_DRV_ERR(device,
		"Unable to get perf counters for bus DCVS\n");
		adreno_dev->ram_cycles_lo_ch1_write = 0;
		}
		}
		} else {
		/* VBIF DDR cycles */
		if (adreno_dev->ram_cycles_lo == 0) {
		ret = adreno_perfcounter_get(adreno_dev,
		@@ -1656,12 +1715,16 @@ static int _adreno_start(struct adreno_device *adreno_dev)
		}
		}
		}
		}

		/* Clear the busy_data stats - we're starting over from scratch */
		adreno_dev->busy_data.gpu_busy = 0;
		adreno_dev->busy_data.vbif_ram_cycles = 0;
		adreno_dev->busy_data.vbif_starved_ram = 0;
		adreno_dev->busy_data.vbif_starved_ram_ch1 = 0;
		adreno_dev->busy_data.bif_ram_cycles = 0;
		adreno_dev->busy_data.bif_ram_cycles_read_ch1 = 0;
		adreno_dev->busy_data.bif_ram_cycles_write_ch0 = 0;
		adreno_dev->busy_data.bif_ram_cycles_write_ch1 = 0;
		adreno_dev->busy_data.bif_starved_ram = 0;
		adreno_dev->busy_data.bif_starved_ram_ch1 = 0;

		/* Restore performance counter registers with saved values */
		adreno_perfcounter_restore(adreno_dev);
		@@ -2495,9 +2558,12 @@ int adreno_soft_reset(struct kgsl_device *device)

		/* Clear the busy_data stats - we're starting over from scratch */
		adreno_dev->busy_data.gpu_busy = 0;
		adreno_dev->busy_data.vbif_ram_cycles = 0;
		adreno_dev->busy_data.vbif_starved_ram = 0;
		adreno_dev->busy_data.vbif_starved_ram_ch1 = 0;
		adreno_dev->busy_data.bif_ram_cycles = 0;
		adreno_dev->busy_data.bif_ram_cycles_read_ch1 = 0;
		adreno_dev->busy_data.bif_ram_cycles_write_ch0 = 0;
		adreno_dev->busy_data.bif_ram_cycles_write_ch1 = 0;
		adreno_dev->busy_data.bif_starved_ram = 0;
		adreno_dev->busy_data.bif_starved_ram_ch1 = 0;

		/* Set the page table back to the default page table */
		adreno_ringbuffer_set_global(adreno_dev, 0);
		@@ -3078,18 +3144,35 @@ static void adreno_power_stats(struct kgsl_device *device,
		if (adreno_dev->ram_cycles_lo != 0)
		ram_cycles = counter_delta(device,
		adreno_dev->ram_cycles_lo,
		&busy->vbif_ram_cycles);
		&busy->bif_ram_cycles);

		if (adreno_has_gbif(adreno_dev)) {
		if (adreno_dev->ram_cycles_lo_ch1_read != 0)
		ram_cycles += counter_delta(device,
		adreno_dev->ram_cycles_lo_ch1_read,
		&busy->bif_ram_cycles_read_ch1);

		if (adreno_dev->ram_cycles_lo_ch0_write != 0)
		ram_cycles += counter_delta(device,
		adreno_dev->ram_cycles_lo_ch0_write,
		&busy->bif_ram_cycles_write_ch0);

		if (adreno_dev->ram_cycles_lo_ch1_write != 0)
		ram_cycles += counter_delta(device,
		adreno_dev->ram_cycles_lo_ch1_write,
		&busy->bif_ram_cycles_write_ch1);
		}

		if (adreno_dev->starved_ram_lo != 0)
		starved_ram = counter_delta(device,
		adreno_dev->starved_ram_lo,
		&busy->vbif_starved_ram);
		&busy->bif_starved_ram);

		if (adreno_has_gbif(adreno_dev)) {
		if (adreno_dev->starved_ram_lo_ch1 != 0)
		starved_ram += counter_delta(device,
		adreno_dev->starved_ram_lo_ch1,
		&busy->vbif_starved_ram_ch1);
		&busy->bif_starved_ram_ch1);
		}

		stats->ram_time = ram_cycles;

drivers/gpu/msm/adreno.h

+17 −4

Original line number	Diff line number	Diff line
		@@ -282,9 +282,12 @@ struct adreno_preemption {

		struct adreno_busy_data {
		unsigned int gpu_busy;
		unsigned int vbif_ram_cycles;
		unsigned int vbif_starved_ram;
		unsigned int vbif_starved_ram_ch1;
		unsigned int bif_ram_cycles;
		unsigned int bif_ram_cycles_read_ch1;
		unsigned int bif_ram_cycles_write_ch0;
		unsigned int bif_ram_cycles_write_ch1;
		unsigned int bif_starved_ram;
		unsigned int bif_starved_ram_ch1;
		unsigned int throttle_cycles[ADRENO_GPMU_THROTTLE_COUNTERS];
		};

		@@ -401,7 +404,14 @@ struct adreno_gpu_core {
		* @pwron_fixup_dwords: Number of dwords in the command buffer
		* @input_work: Work struct for turning on the GPU after a touch event
		* @busy_data: Struct holding GPU VBIF busy stats
		* @ram_cycles_lo: Number of DDR clock cycles for the monitor session
		* @ram_cycles_lo: Number of DDR clock cycles for the monitor session (Only
		* DDR channel 0 read cycles in case of GBIF)
		* @ram_cycles_lo_ch1_read: Number of DDR channel 1 Read clock cycles for
		* the monitor session
		* @ram_cycles_lo_ch0_write: Number of DDR channel 0 Write clock cycles for
		* the monitor session
		* @ram_cycles_lo_ch1_write: Number of DDR channel 0 Write clock cycles for
		* the monitor session
		* @starved_ram_lo: Number of cycles VBIF/GBIF is stalled by DDR (Only channel 0
		* stall cycles in case of GBIF)
		* @starved_ram_lo_ch1: Number of cycles GBIF is stalled by DDR channel 1
		@@ -465,6 +475,9 @@ struct adreno_device {
		struct work_struct input_work;
		struct adreno_busy_data busy_data;
		unsigned int ram_cycles_lo;
		unsigned int ram_cycles_lo_ch1_read;
		unsigned int ram_cycles_lo_ch0_write;
		unsigned int ram_cycles_lo_ch1_write;
		unsigned int starved_ram_lo;
		unsigned int starved_ram_lo_ch1;
		unsigned int perfctr_pwr_lo;

drivers/gpu/msm/adreno_a6xx.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -3013,7 +3013,8 @@ static void a6xx_platform_setup(struct adreno_device *adreno_dev)

		a6xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_VBIF_PWR].regs =
		a6xx_perfcounters_gbif_pwr;
		a6xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_VBIF].reg_count
		a6xx_perfcounter_groups[
		KGSL_PERFCOUNTER_GROUP_VBIF_PWR].reg_count
		= ARRAY_SIZE(a6xx_perfcounters_gbif_pwr);

		gpudev->vbif_xin_halt_ctrl0_mask =