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Commit e7958bb9 authored by Ralf Baechle's avatar Ralf Baechle Committed by
Browse files

MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1. 


    
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 571e0bed

arch/mips/kernel/cpu-probe.c

+6 −6
Original line number Diff line number Diff line
@@ -447,10 +447,10 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c) 
	isa = (config0 & MIPS_CONF_AT) >> 13;

	switch (isa) {

	case 0:

		c->isa_level = MIPS_CPU_ISA_M32;

		c->isa_level = MIPS_CPU_ISA_M32R1;

		break;

	case 2:

		c->isa_level = MIPS_CPU_ISA_M64;

		c->isa_level = MIPS_CPU_ISA_M64R1;

		break;

	default:

		panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
@@ -568,7 +568,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c) 
		break;

	case PRID_IMP_34K:

		c->cputype = CPU_34K;

		c->isa_level = MIPS_CPU_ISA_M32;

		c->isa_level = MIPS_CPU_ISA_M32R1;

		break;

	}

}
@@ -647,7 +647,7 @@ static inline void cpu_probe_philips(struct cpuinfo_mips *c) 
	switch (c->processor_id & 0xff00) {

	case PRID_IMP_PR4450:

		c->cputype = CPU_PR4450;

		c->isa_level = MIPS_CPU_ISA_M32;

		c->isa_level = MIPS_CPU_ISA_M32R1;

		break;

	default:

		panic("Unknown Philips Core!"); /* REVISIT: die? */
@@ -690,8 +690,8 @@ __init void cpu_probe(void) 
	if (c->options & MIPS_CPU_FPU) {

		c->fpu_id = cpu_get_fpu_id();



		if (c->isa_level == MIPS_CPU_ISA_M32 ||

		    c->isa_level == MIPS_CPU_ISA_M64) {

		if (c->isa_level == MIPS_CPU_ISA_M32R1 ||

		    c->isa_level == MIPS_CPU_ISA_M64R1) {

			if (c->fpu_id & MIPS_FPIR_3D)

				c->ases |= MIPS_ASE_MIPS3D;

		}

arch/mips/kernel/time.c

+1 −1
Original line number Diff line number Diff line
@@ -628,7 +628,7 @@ void __init time_init(void) 
			mips_hpt_init = c0_hpt_init;

		}



		if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32) ||

		if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32R1) ||

			 (current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||

			 (current_cpu_data.isa_level == MIPS_CPU_ISA_II))

			/*

arch/mips/mm/c-r4k.c

+2 −2
Original line number Diff line number Diff line
@@ -1183,8 +1183,8 @@ static void __init setup_scache(void) 
	if (!sc_present)

		return;



	if ((c->isa_level == MIPS_CPU_ISA_M32 ||

	     c->isa_level == MIPS_CPU_ISA_M64) &&

	if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||

	     c->isa_level == MIPS_CPU_ISA_M64R1) &&

	    !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))

		panic("Dunno how to handle MIPS32 / MIPS64 second level cache");

include/asm-mips/cpu.h

+7 −10
Original line number Diff line number Diff line
@@ -202,18 +202,15 @@ 
 * ISA Level encodings

 *

 */

#define MIPS_CPU_ISA_64BIT	0x00008000



#define MIPS_CPU_ISA_I		0x00000001

#define MIPS_CPU_ISA_II		0x00000002

#define MIPS_CPU_ISA_III	0x00008003

#define MIPS_CPU_ISA_IV		0x00008004

#define MIPS_CPU_ISA_V		0x00008005

#define MIPS_CPU_ISA_M32	0x00000020

#define MIPS_CPU_ISA_M64	0x00008040



/*

 * Bit 15 encodes if an ISA level supports 64-bit operations.

 */

#define MIPS_CPU_ISA_64BIT	0x00008000

#define MIPS_CPU_ISA_III	(0x00000003 | MIPS_CPU_ISA_64BIT)

#define MIPS_CPU_ISA_IV		(0x00000004 | MIPS_CPU_ISA_64BIT)

#define MIPS_CPU_ISA_V		(0x00000005 | MIPS_CPU_ISA_64BIT)

#define MIPS_CPU_ISA_M32R1	0x00000020

#define MIPS_CPU_ISA_M64R1	(0x00000040 | MIPS_CPU_ISA_64BIT)



/*

 * CPU Option encodings