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Commit e7841be5 authored by Huacai Chen's avatar Huacai Chen Committed by Ralf Baechle
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MIPS: Add Loongson-3B support 



Loongson-3B is a 8-cores processor. In general it looks like there are
two Loongson-3A integrated in one chip: 8 cores are separated into two
groups (two NUMA node), each node has its own local memory.

Of course there are some differences between one Loongson-3B and two
Loongson-3A. E.g., the base addresses of IPI registers of each node are
not the same; Loongson-3A use ChipConfig register to enable/disable
clock, but Loongson-3B use FreqControl register instead.

There are two revision of Loongson-3B, the first revision is called as
Loongson-3B1000, whose frequency is 1GHz and has a PRid 0x6306, the
second revision is called as Loongson-3B1500, whose frequency is 1.5GHz
and has a PRid 0x6307. Both revisions has a bug that clock cannot be
disabled at runtime, but this will be fixed in future.

Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7188/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 1ff1ad6b

arch/mips/include/asm/cpu.h

+2 −0
Original line number Diff line number Diff line
@@ -233,6 +233,8 @@ 
#define PRID_REV_LOONGSON2E	0x0002

#define PRID_REV_LOONGSON2F	0x0003

#define PRID_REV_LOONGSON3A	0x0005

#define PRID_REV_LOONGSON3B_R1	0x0006

#define PRID_REV_LOONGSON3B_R2	0x0007



/*

 * Older processors used to encode processor version and revision in two

arch/mips/include/asm/mach-loongson/boot_param.h

+1 −0
Original line number Diff line number Diff line
@@ -163,4 +163,5 @@ struct loongson_system_configuration { 


extern struct efi_memory_map_loongson *loongson_memmap;

extern struct loongson_system_configuration loongson_sysconf;

extern int cpuhotplug_workaround;

#endif

arch/mips/include/asm/mach-loongson/loongson.h

+4 −0
Original line number Diff line number Diff line
@@ -255,6 +255,10 @@ static inline void do_perfcnt_IRQ(void) 
extern u64 loongson_chipcfg[MAX_PACKAGES];

#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))



/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */

extern u64 loongson_freqctrl[MAX_PACKAGES];

#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))



/* pcimap */



#define LOONGSON_PCIMAP_PCIMAP_LO0	0x0000003f

arch/mips/kernel/cpu-probe.c

+6 −0
Original line number Diff line number Diff line
@@ -740,6 +740,12 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 
			__cpu_name[cpu] = "ICT Loongson-3";

			set_elf_platform(cpu, "loongson3a");

			break;

		case PRID_REV_LOONGSON3B_R1:

		case PRID_REV_LOONGSON3B_R2:

			c->cputype = CPU_LOONGSON3;

			__cpu_name[cpu] = "ICT Loongson-3";

			set_elf_platform(cpu, "loongson3b");

			break;

		}



		set_isa(c, MIPS_CPU_ISA_III);

arch/mips/loongson/common/env.c

+30 −1
Original line number Diff line number Diff line
@@ -28,6 +28,10 @@ struct efi_memory_map_loongson *loongson_memmap; 
struct loongson_system_configuration loongson_sysconf;



u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};

u64 loongson_freqctrl[MAX_PACKAGES];



unsigned long long smp_group[4];

int cpuhotplug_workaround = 0;



#define parse_even_earlier(res, option, p)				\

do {									\
@@ -82,10 +86,32 @@ void __init prom_init_env(void) 
	if (ecpu->cputype == Loongson_3A) {

		loongson_sysconf.cores_per_node = 4;

		loongson_sysconf.cores_per_package = 4;

		smp_group[0] = 0x900000003ff01000;

		smp_group[1] = 0x900010003ff01000;

		smp_group[2] = 0x900020003ff01000;

		smp_group[3] = 0x900030003ff01000;

		loongson_chipcfg[0] = 0x900000001fe00180;

		loongson_chipcfg[1] = 0x900010001fe00180;

		loongson_chipcfg[2] = 0x900020001fe00180;

		loongson_chipcfg[3] = 0x900030001fe00180;

		loongson_sysconf.ht_control_base = 0x90000EFDFB000000;

	} else if (ecpu->cputype == Loongson_3B) {

		loongson_sysconf.cores_per_node = 4; /* One chip has 2 nodes */

		loongson_sysconf.cores_per_package = 8;

		smp_group[0] = 0x900000003ff01000;

		smp_group[1] = 0x900010003ff05000;

		smp_group[2] = 0x900020003ff09000;

		smp_group[3] = 0x900030003ff0d000;

		loongson_chipcfg[0] = 0x900000001fe00180;

		loongson_chipcfg[1] = 0x900020001fe00180;

		loongson_chipcfg[2] = 0x900040001fe00180;

		loongson_chipcfg[3] = 0x900060001fe00180;

		loongson_freqctrl[0] = 0x900000001fe001d0;

		loongson_freqctrl[1] = 0x900020001fe001d0;

		loongson_freqctrl[2] = 0x900040001fe001d0;

		loongson_freqctrl[3] = 0x900060001fe001d0;

		loongson_sysconf.ht_control_base = 0x90001EFDFB000000;

		cpuhotplug_workaround = 1;

	} else {

		loongson_sysconf.cores_per_node = 1;

		loongson_sysconf.cores_per_package = 1;
@@ -111,7 +137,6 @@ void __init prom_init_env(void) 
	loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;

	loongson_sysconf.suspend_addr = boot_p->reset_system.DoSuspend;



	loongson_sysconf.ht_control_base = 0x90000EFDFB000000;

	loongson_sysconf.vgabios_addr = boot_p->efi.smbios.vga_bios;

	pr_debug("Shutdown Addr: %llx, Restart Addr: %llx, VBIOS Addr: %llx\n",

		loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr,
@@ -129,6 +154,10 @@ void __init prom_init_env(void) 
		case PRID_REV_LOONGSON3A:

			cpu_clock_freq = 900000000;

			break;

		case PRID_REV_LOONGSON3B_R1:

		case PRID_REV_LOONGSON3B_R2:

			cpu_clock_freq = 1000000000;

			break;

		default:

			cpu_clock_freq = 100000000;

			break;