Commit e7824015 authored Feb 15, 2016 by Andy Shevchenko Committed by Greg Kroah-Hartman Mar 07, 2016

serial: 8250_pci: all known Braswell ports are 1 channel



There is no need to have channel offset defined since all BayTrail and Braswell
ports are 1 channel. Remove unneeded definition.

While here, remove comment which has no value.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 3f64b1d3

drivers/tty/serial/8250/8250_pci.c

+0 −5

Original line number	Diff line number	Diff line
		@@ -3698,15 +3698,10 @@ static struct pciserial_board pci_boards[] = {
		.base_baud = 921600,
		.reg_shift = 2,
		},
		/*
		* Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
		* but is overridden by byt_set_termios.
		*/
		[pbn_byt] = {
		.flags = FL_BASE0,
		.num_ports = 1,
		.base_baud = 2764800,
		.uart_offset = 0x80,
		.reg_shift = 2,
		},
		[pbn_qrk] = {