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Commit e6ef01c2 authored by Gopikrishnaiah Anandan's avatar Gopikrishnaiah Anandan Committed by Gerrit - the friendly Code Review server
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drm/msm/sde: Add support for gamut programming with AHB 



If sde block supports reg dma, luts can be programmed using the lut dma.
For sde blocks which don't support reg dma, programming has to be done
via ahb interface. Change adds support for ahb programming.

Change-Id: Ie4bc725d128f0f491dbd9a3e422a8a87a6aa26a0
Signed-off-by: default avatarGopikrishnaiah Anandan <agopik@codeaurora.org>
parent fbf75398

drivers/gpu/drm/msm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ msm_drm-y := \ 
	sde_dbg_evtlog.o \

	sde_io_util.o \

	sde/sde_hw_reg_dma_v1_color_proc.o \

	sde/sde_hw_color_proc_v4.o \



# use drm gpu driver only if qcom_kgsl driver not available

ifneq ($(CONFIG_QCOM_KGSL),y)

drivers/gpu/drm/msm/sde/sde_hw_color_proc_v4.c

0 → 100644
+111 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <drm/msm_drm_pp.h>

#include "sde_hw_color_proc_common_v4.h"

#include "sde_hw_color_proc_v4.h"



static int sde_write_3d_gamut(struct sde_hw_blk_reg_map *hw,

		struct drm_msm_3d_gamut *payload, u32 base,

		u32 *opcode)

{

	u32 reg, tbl_len, tbl_off, scale_off, i, j;

	u32 *scale_data;



	if (!payload || !opcode || !hw) {

		DRM_ERROR("invalid payload %pK opcode %pK hw %pK\n",

			payload, opcode, hw);

		return -EINVAL;

	}



	switch (payload->mode) {

	case GAMUT_3D_MODE_17:

		tbl_len = GAMUT_3D_MODE17_TBL_SZ;

		tbl_off = 0;

		scale_off = GAMUT_SCALEA_OFFSET_OFF;

		*opcode = gamut_mode_17 << 2;

		break;

	case GAMUT_3D_MODE_13:

		*opcode = (*opcode & (BIT(4) - 1)) >> 2;

		if (*opcode == gamut_mode_13a)

			*opcode = gamut_mode_13b;

		else

			*opcode = gamut_mode_13a;

		tbl_len = GAMUT_3D_MODE13_TBL_SZ;

		tbl_off = (*opcode == gamut_mode_13a) ? 0 :

			GAMUT_MODE_13B_OFF;

		scale_off = (*opcode == gamut_mode_13a) ?

			GAMUT_SCALEA_OFFSET_OFF : GAMUT_SCALEB_OFFSET_OFF;

		*opcode <<= 2;

		break;

	case GAMUT_3D_MODE_5:

		*opcode = gamut_mode_5 << 2;

		*opcode |= GAMUT_MAP_EN;

		tbl_len = GAMUT_3D_MODE5_TBL_SZ;

		tbl_off = 0;

		scale_off = GAMUT_SCALEB_OFFSET_OFF;

		break;

	default:

		DRM_ERROR("invalid mode %d\n", payload->mode);

		return -EINVAL;

	}



	if (payload->flags & GAMUT_3D_MAP_EN)

		*opcode |= GAMUT_MAP_EN;

	*opcode |= GAMUT_EN;



	for (i = 0; i < GAMUT_3D_TBL_NUM; i++) {

		reg = GAMUT_TABLE0_SEL << i;

		reg |= ((tbl_off) & (BIT(11) - 1));

		SDE_REG_WRITE(hw, base + GAMUT_TABLE_SEL_OFF, reg);

		for (j = 0; j < tbl_len; j++) {

			SDE_REG_WRITE(hw, base + GAMUT_LOWER_COLOR_OFF,

					payload->col[i][j].c2_c1);

			SDE_REG_WRITE(hw, base + GAMUT_UPPER_COLOR_OFF,

					payload->col[i][j].c0);

		}

	}



	if ((*opcode & GAMUT_MAP_EN)) {

		scale_data = &payload->scale_off[0][0];

		tbl_off = base + scale_off;

		tbl_len = GAMUT_3D_SCALE_OFF_TBL_NUM * GAMUT_3D_SCALE_OFF_SZ;

		for (i = 0; i < tbl_len; i++)

			SDE_REG_WRITE(hw, tbl_off + (i * sizeof(u32)),

					scale_data[i]);

	}

	SDE_REG_WRITE(hw, base, *opcode);

	return 0;

}



void sde_setup_dspp_3d_gamutv4(struct sde_hw_dspp *ctx, void *cfg)

{

	struct drm_msm_3d_gamut *payload;

	struct sde_hw_cp_cfg *hw_cfg = cfg;

	u32 op_mode;



	if (!ctx || !cfg) {

		DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);

		return;

	}



	op_mode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->gamut.base);

	if (!hw_cfg->payload) {

		DRM_DEBUG_DRIVER("disable gamut feature\n");

		SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->gamut.base, 0);

		return;

	}



	payload = hw_cfg->payload;

	sde_write_3d_gamut(&ctx->hw, payload, ctx->cap->sblk->gamut.base,

		&op_mode);



}

drivers/gpu/drm/msm/sde/sde_hw_color_proc_v4.h

0 → 100644
+26 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#ifndef _SDE_HW_COLOR_PROC_V4_H_

#define _SDE_HW_COLOR_PROC_V4_H_



#include "sde_hw_util.h"

#include "sde_hw_catalog.h"

#include "sde_hw_dspp.h"

/**

 * sde_setup_dspp_3d_gamutv4 - Function for 3d gamut v4 version feature

 *                             programming.

 * @ctx: dspp ctx pointer

 * @cfg: pointer to sde_hw_cp_cfg

 */

void sde_setup_dspp_3d_gamutv4(struct sde_hw_dspp *ctx, void *cfg);



#endif /* _SDE_HW_COLOR_PROC_V4_H_ */

drivers/gpu/drm/msm/sde/sde_hw_color_processing.h

+1 −0
Original line number Diff line number Diff line
@@ -15,5 +15,6 @@ 


#include "sde_hw_color_processing_v1_7.h"

#include "sde_hw_reg_dma_v1_color_proc.h"

#include "sde_hw_color_proc_v4.h"



#endif

drivers/gpu/drm/msm/sde/sde_hw_dspp.c

+3 −0
Original line number Diff line number Diff line
@@ -74,6 +74,9 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) 
				if (!ret)

					c->ops.setup_gamut =

						reg_dmav1_setup_dspp_3d_gamutv4;

				else

					c->ops.setup_gamut =

						sde_setup_dspp_3d_gamutv4;

			}

			break;

		case SDE_DSPP_GC: