Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e6cd6dc1 authored by Paulo Zanoni's avatar Paulo Zanoni
Browse files

drm/i915: check for FBC planes in the same place as the pipes 



This moves the pre-gen4 check from update() to enable(). The HAS_DDI
in the original code is not needed since only gen 2/3 have the plane
swapping code.

v2: Rebase.
v3: Extract fbc_on_plane_a_only() (Chris).

Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
parent c5ecd469

drivers/gpu/drm/i915/intel_fbc.c

+8 −6
Original line number Diff line number Diff line
@@ -51,6 +51,11 @@ static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) 
	return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8;

}



static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)

{

	return INTEL_INFO(dev_priv)->gen < 4;

}



/*

 * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the

 * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
@@ -514,6 +519,9 @@ static bool crtc_can_fbc(struct intel_crtc *crtc) 
	if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)

		return false;



	if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)

		return false;



	return true;

}
@@ -802,12 +810,6 @@ static void __intel_fbc_update(struct intel_crtc *crtc) 
		goto out_disable;

	}



	if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) &&

	    crtc->plane != PLANE_A) {

		set_no_fbc_reason(dev_priv, "FBC unsupported on plane");

		goto out_disable;

	}



	/* The use of a CPU fence is mandatory in order to detect writes

	 * by the CPU to the scanout and trigger updates to the FBC.

	 */