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Commit e69dc598 authored by Gopikrishnaiah Anandan's avatar Gopikrishnaiah Anandan
Browse files

drm/msm/sde: Initialize the mmu contexts early during probe 



Reg dma block will allocate the memory during the probe for supported
features. Sde mmu context banks should be initialized before the reg dma
init is called. Change moves the smmu init to the start of the probe.

Change-Id: Id38db251afdb855339e8d5a4bcb9e3464bbe7ae2
Signed-off-by: default avatarGopikrishnaiah Anandan <agopik@codeaurora.org>
parent d70773af

drivers/gpu/drm/msm/sde/sde_hw_dspp.c

+2 −0
Original line number Diff line number Diff line
@@ -151,5 +151,7 @@ struct sde_hw_dspp *sde_hw_dspp_init(enum sde_dspp idx, 


void sde_hw_dspp_destroy(struct sde_hw_dspp *dspp)

{

	if (dspp)

		reg_dmav1_deinit_dspp_ops(dspp->idx);

	kfree(dspp);

}

drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c

+23 −0
Original line number Diff line number Diff line
@@ -553,3 +553,26 @@ void reg_dmav1_setup_dspp_gcv18(struct sde_hw_dspp *ctx, void *cfg) 
			BIT(0));

	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->gc.base, reg);

}



int reg_dmav1_deinit_dspp_ops(enum sde_dspp idx)

{

	int i;

	struct sde_hw_reg_dma_ops *dma_ops;



	dma_ops = sde_reg_dma_get_ops();

	if (IS_ERR_OR_NULL(dma_ops))

		return -ENOTSUPP;



	if (idx >= DSPP_MAX) {

		DRM_ERROR("invalid dspp idx %x max %xd\n", idx, DSPP_MAX);

		return -EINVAL;

	}



	for (i = 0; i < REG_DMA_FEATURES_MAX; i++) {

		if (!dspp_buf[i][idx])

			continue;

		dma_ops->dealloc_reg_dma(dspp_buf[i][idx]);

		dspp_buf[i][idx] = NULL;

	}

	return 0;

}

drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h

+7 −0
Original line number Diff line number Diff line
@@ -51,4 +51,11 @@ void reg_dmav1_setup_dspp_3d_gamutv4(struct sde_hw_dspp *ctx, void *cfg); 
 * @cfg: pointer to struct sde_hw_cp_cfg

 */

void reg_dmav1_setup_dspp_gcv18(struct sde_hw_dspp *ctx, void *cfg);



/**

 * reg_dmav1_deinit_dspp_ops() - deinitialize the dspp feature op for sde v4

 *                               which were initialized.

 * @idx: dspp idx

 */

int reg_dmav1_deinit_dspp_ops(enum sde_dspp idx);

#endif /* _SDE_HW_REG_DMA_V1_COLOR_PROC_H */

drivers/gpu/drm/msm/sde/sde_kms.c

+10 −9
Original line number Diff line number Diff line
@@ -1470,6 +1470,16 @@ static int sde_kms_hw_init(struct msm_kms *kms) 


	sde_dbg_init_dbg_buses(sde_kms->core_rev);



	/*

	 * Now we need to read the HW catalog and initialize resources such as

	 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc

	 */

	rc = _sde_kms_mmu_init(sde_kms);

	if (rc) {

		SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);

		goto power_error;

	}



	/* Initialize reg dma block which is a singleton */

	rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,

			sde_kms->dev);
@@ -1519,15 +1529,6 @@ static int sde_kms_hw_init(struct msm_kms *kms) 
		sde_kms->iclient = NULL;

	}



	/*

	 * Now we need to read the HW catalog and initialize resources such as

	 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc

	 */

	rc = _sde_kms_mmu_init(sde_kms);

	if (rc) {

		SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);

		goto power_error;

	}



	rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,

			&priv->phandle, priv->pclient, "core_clk");