Commit e606e035 authored Dec 07, 2015 by Frederic Barrat Committed by Michael Ellerman Dec 08, 2015

cxl: Set endianess of kernel contexts



A process element (defined in CAIA) keeps track of the endianess of
contexts through the Little Endian (LE) bit of the State Register. It
is currently set for user contexts, but was somehow forgotten for
kernel contexts, so this patch fixes it.
It could lead to erratic behavior from an AFU when the context is
attached through the kernel API.

Fixes: 2f663527 ("cxl: Configure PSL for kernel contexts and merge code")
Cc: stable@vger.kernel.org # 4.2+
Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Suggested-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

parent 25642e14

drivers/misc/cxl/native.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -497,6 +497,7 @@ static u64 calculate_sr(struct cxl_context *ctx)
		{
		u64 sr = 0;

		set_endian(sr);
		if (ctx->master)
		sr \|= CXL_PSL_SR_An_MP;
		if (mfspr(SPRN_LPCR) & LPCR_TC)
		@@ -506,7 +507,6 @@ static u64 calculate_sr(struct cxl_context *ctx)
		sr \|= CXL_PSL_SR_An_HV;
		} else {
		sr \|= CXL_PSL_SR_An_PR \| CXL_PSL_SR_An_R;
		set_endian(sr);
		sr &= ~(CXL_PSL_SR_An_HV);
		if (!test_tsk_thread_flag(current, TIF_32BIT))
		sr \|= CXL_PSL_SR_An_SF;