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Commit e5766aea authored by Jonas Gorski's avatar Jonas Gorski Committed by Ralf Baechle
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MIPS: BCM63XX: Add basic BCM6328 support



This includes CPU speed, memory size detection and working UART, but
lacking the appropriate drivers, no support for attached flash.

Signed-off-by: default avatarJonas Gorski <jonas.gorski@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Maxime Bizon <mbizon@freebox.fr>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Kevin Cernekee <cernekee@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/3951/


Reviewed-by: default avatarFlorian Fainelli <florian@openwrt.org>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 288752a8
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+3 −0
Original line number Diff line number Diff line
menu "CPU support"
	depends on BCM63XX

config BCM63XX_CPU_6328
	bool "support 6328 CPU"

config BCM63XX_CPU_6338
	bool "support 6338 CPU"
	select HW_HAS_PCI
+9 −3
Original line number Diff line number Diff line
@@ -708,9 +708,15 @@ void __init board_prom_init(void)
	char cfe_version[32];
	u32 val;

	/* read base address of boot chip select (0) */
	/* read base address of boot chip select (0)
	 * 6328 does not have MPI but boots from a fixed address
	 */
	if (BCMCPU_IS_6328())
		val = 0x18000000;
	else {
		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
		val &= MPI_CSBASE_BASE_MASK;
	}
	boot_addr = (u8 *)KSEG1ADDR(val);

	/* dump cfe version */
+43 −0
Original line number Diff line number Diff line
@@ -29,6 +29,14 @@ static u16 bcm63xx_cpu_rev;
static unsigned int bcm63xx_cpu_freq;
static unsigned int bcm63xx_memory_size;

static const unsigned long bcm6328_regs_base[] = {
	__GEN_CPU_REGS_TABLE(6328)
};

static const int bcm6328_irqs[] = {
	__GEN_CPU_IRQ_TABLE(6328)
};

static const unsigned long bcm6338_regs_base[] = {
	__GEN_CPU_REGS_TABLE(6338)
};
@@ -99,6 +107,33 @@ unsigned int bcm63xx_get_memory_size(void)
static unsigned int detect_cpu_clock(void)
{
	switch (bcm63xx_get_cpu_id()) {
	case BCM6328_CPU_ID:
	{
		unsigned int tmp, mips_pll_fcvo;

		tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
		mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
				>> STRAPBUS_6328_FCVO_SHIFT;

		switch (mips_pll_fcvo) {
		case 0x12:
		case 0x14:
		case 0x19:
			return 160000000;
		case 0x1c:
			return 192000000;
		case 0x13:
		case 0x15:
			return 200000000;
		case 0x1a:
			return 384000000;
		case 0x16:
			return 400000000;
		default:
			return 320000000;
		}

	}
	case BCM6338_CPU_ID:
		/* BCM6338 has a fixed 240 Mhz frequency */
		return 240000000;
@@ -170,6 +205,9 @@ static unsigned int detect_memory_size(void)
	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
	u32 val;

	if (BCMCPU_IS_6328())
		return bcm_ddr_readl(DDR_CSEND_REG) << 24;

	if (BCMCPU_IS_6345()) {
		val = bcm_sdram_readl(SDRAM_MBASE_REG);
		return (val * 8 * 1024 * 1024);
@@ -237,6 +275,11 @@ void __init bcm63xx_cpu_init(void)
			u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);

			switch (chip_id) {
			case BCM6328_CPU_ID:
				expected_cpu_id = BCM6328_CPU_ID;
				bcm63xx_regs_base = bcm6328_regs_base;
				bcm63xx_irqs = bcm6328_irqs;
				break;
			case BCM6368_CPU_ID:
				expected_cpu_id = BCM6368_CPU_ID;
				bcm63xx_regs_base = bcm6368_regs_base;
+6 −0
Original line number Diff line number Diff line
@@ -60,6 +60,12 @@ static int __init bcm63xx_detect_flash_type(void)
	u32 val;

	switch (bcm63xx_get_cpu_id()) {
	case BCM6328_CPU_ID:
		val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
		if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
			return BCM63XX_FLASH_TYPE_SERIAL;
		else
			return BCM63XX_FLASH_TYPE_NAND;
	case BCM6338_CPU_ID:
	case BCM6345_CPU_ID:
	case BCM6348_CPU_ID:
+1 −1
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ int __init bcm63xx_spi_register(void)
{
	struct clk *periph_clk;

	if (BCMCPU_IS_6345())
	if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
		return -ENODEV;

	periph_clk = clk_get(NULL, "periph");
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