Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e50bf385 authored by Maurus Cuelenaere's avatar Maurus Cuelenaere Committed by Greg Kroah-Hartman
Browse files

USB: s3c-hsotg: Add support for external USB clock 



The PLL that drives the USB clock supports 3 input clocks: 12, 24 and 48Mhz.
This patch adds support to the USB driver for setting the correct register bit
according to the given clock.

This depends on the following patch:
[PATCH] ARM: S3C64XX: Add USB external clock definition

Signed-off-by: default avatarMaurus Cuelenaere <mcuelenaere@gmail.com>
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent a33e7136

drivers/usb/gadget/s3c-hsotg.c

+19 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include <linux/delay.h>

#include <linux/io.h>

#include <linux/slab.h>

#include <linux/clk.h>



#include <linux/usb/ch9.h>

#include <linux/usb/gadget.h>
@@ -2798,6 +2799,7 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg, 
 */

static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)

{

	struct clk *xusbxti;

	u32 osc;



	writel(0, S3C_PHYPWR);
@@ -2805,6 +2807,23 @@ static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg) 


	osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;



	xusbxti = clk_get(hsotg->dev, "xusbxti");

	if (xusbxti && !IS_ERR(xusbxti)) {

		switch (clk_get_rate(xusbxti)) {

		case 12*MHZ:

			osc |= S3C_PHYCLK_CLKSEL_12M;

			break;

		case 24*MHZ:

			osc |= S3C_PHYCLK_CLKSEL_24M;

			break;

		default:

		case 48*MHZ:

			/* default reference clock */

			break;

		}

		clk_put(xusbxti);

	}



	writel(osc | 0x10, S3C_PHYCLK);



	/* issue a full set of resets to the otg and core */