Commit e4fd17af authored Mar 28, 2012 by Daniel Kurtz Committed by Daniel Vetter Mar 28, 2012

drm/i915/intel_i2c: assign HDMI port D to pin pair 6

According to i915 documentation [1], "Port D" (DP/HDMI Port D) is
actually gmbus pin pair 6 (gmbus0.2:0 == 110b GPIOF), not 7 (111b).
Pin pair 7 is a reserved pair.

[1] Documentation for [DevSNB+] and [DevIBX], as found on
http://intellinuxgraphics.org:

[DevSNB+]:
http://intellinuxgraphics.org/documentation/SNB/IHD_OS_Vol3_Part3.pdf
 Section 2.2.2 lists the 6 gmbus ports (gpio pin pairs):
    [ 5: HDMI/DPD, 4: HDMIB, 3: HDMI/DPC, 2: LVDS, 1: SSC, 0: VGA ]
 2.2.2.1 lists the GPIO registers to control these 6 ports.
 2.2.3.1 lists the mapping between 5 of these gmbus ports and the 3
 Pin_Pair_Select bits (of the GMBUS0 register).  This table is missing
 HDMIB (port 101).

[DevIBX]: http://intellinuxgraphics.org/IHD_OS_Vol3_Part3r2.pdf


 Section 2.2.2 lists the same 6 gmbus ports plus two 'reserved' gpio
 ports.
 2.2.2.1 lists 8 GPIO registers... however, it says the size of the
 block is 6x32, which implies that those 2 reserved GPIO registers
 (GPIO_6 & GPIO_7) don't actually exist (or are irrelevant).
 2.2.3.1 lists the mapping between the 6 named gmbus ports and the 3
 Pin_Pair_Select bits (of the GMBUS0 register).  This table has HDMIB.

Note: the "reserved" and "disabled" pairs do not actually map to a
physical pair of pins, nor GPIO regs and shouldn't be initialized or used.
Fixing this is left for a later patch.

This bug had not been noticed earlier for two reasons:
 1) Until recently, "gmbus" mode was disabled - all transfers actually
    used "bit-bang" mode on GPIO port 5 (the "HDMI/DPD CTLDATA/CLK"
    pair), at register 0x5024 (defined as GPIOF i915_reg.h).
    Since this is the correct pair of pins for HDMI1, transfers succeed.

 2) Even if gmbus mode is re-enabled, the first attempted transaction
    will fail because it tries to use the wrong ("Reserved") pin pair.
    However, the driver immediately falls back again to the bit-bang
    method, which correctly uses GPIOF, so again, transfers succeed.

However, if gmbus mode is re-enabled and the GPIO fall-back mode is
disabled, then reading an attached monitor's EDID fail.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent 874e3cc9

drivers/gpu/drm/i915/i915_reg.h

+3 −3

Original line number	Diff line number	Diff line
		@@ -742,8 +742,8 @@
		#define GMBUS_PORT_PANEL 3
		#define GMBUS_PORT_DPC 4 /* HDMIC */
		#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
		/* 6 reserved */
		#define GMBUS_PORT_DPD 7 /* HDMID */
		#define GMBUS_PORT_DPD 6 /* HDMID */
		#define GMBUS_PORT_RESERVED 7 /* 7 reserved */
		#define GMBUS_NUM_PORTS 8
		#define GMBUS1 0x5104 /* command/status */
		#define GMBUS_SW_CLR_INT (1<<31)

drivers/gpu/drm/i915/intel_i2c.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -148,8 +148,8 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
		GPIOC,
		GPIOD,
		GPIOE,
		0,
		GPIOF,
		0,
		};
		struct i2c_algo_bit_data *algo;

		@@ -385,8 +385,8 @@ int intel_setup_gmbus(struct drm_device *dev)
		"panel",
		"dpc",
		"dpb",
		"reserved",
		"dpd",
		"reserved",
		};
		struct drm_i915_private *dev_priv = dev->dev_private;
		int ret, i;