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Commit e48ec876 authored by Tony Truong's avatar Tony Truong
Browse files

msm: pcie: update mask and linkdown check in PCIe read/write API 



The current check for linkdown does not suffice if the default
value of that register is 0xffffffff. PCIe bus driver needs to
also read the device/vendor ID of the client to confirm if it
is really a linkdown. Update the mask method to be compatible
with 64-bit architecture.

Change-Id: Ibe51dff50ff010260a750d73498333ee830fca2c
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent f9f5ff09

drivers/pci/host/pci-msm.c

+12 −7
Original line number Diff line number Diff line
@@ -3314,7 +3314,7 @@ static inline int msm_pcie_oper_conf(struct pci_bus *bus, u32 devfn, int oper, 


	word_offset = where & ~0x3;

	byte_offset = where & 0x3;

	mask = (~0 >> (8 * (4 - size))) << (8 * byte_offset);

	mask = ((u32)~0 >> (8 * (4 - size))) << (8 * byte_offset);



	if (rc || !dev->enumerated) {

		config_base = rc ? dev->dm_core : dev->conf;
@@ -3349,12 +3349,17 @@ static inline int msm_pcie_oper_conf(struct pci_bus *bus, u32 devfn, int oper, 
		writel_relaxed(wr_val, config_base + word_offset);

		wmb(); /* ensure config data is written to hardware register */



		if (rd_val == PCIE_LINK_DOWN)

		if (dev->shadow_en) {

			if (rd_val == PCIE_LINK_DOWN &&

				(readl_relaxed(config_base) == PCIE_LINK_DOWN))

				PCIE_ERR(dev,

					"Read of RC%d %d:0x%02x + 0x%04x[%d] is all FFs\n",

				rc_idx, bus->number, devfn, where, size);

		else if (dev->shadow_en)

			msm_pcie_save_shadow(dev, word_offset, wr_val, bdf, rc);

					rc_idx, bus->number, devfn,

					where, size);

			else

				msm_pcie_save_shadow(dev, word_offset, wr_val,

					bdf, rc);

		}



		PCIE_DBG3(dev,

			"RC%d %d:0x%02x + 0x%04x[%d] <- 0x%08x; rd 0x%08x val 0x%08x\n",