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Commit e3ed1a34 authored by Raja Mallik's avatar Raja Mallik
Browse files

Merge remote-tracking branch 'dev/msm-4.14' into msm-4.9 08/19 



* commit '65130d2ad231cd3fd65e076e45b4593b9555f5b1':

  msm: camera: cam_isp: Change default fps value
  ARM: dts: msm: Add dtsi string support for bindings
  msm: camera: isp: Added PPI driver functionality
  msm: camera: isp: Log information during IFE acquire failure
  msm: camera: cam_isp: Recovery after IRQ delayed
  msm: camera: isp: Add fps Blob support
  msm: camera: isp: Enable pixel_format_measurement in CSID
  msm: camera: isp: Handle wait and active list during flush all
  msm: camera: isp: Add irq status prints to CAM_ERR

Change-Id: I43ce3f6daaa91302e8b1db030b7953372b463606
Signed-off-by: default avatarRaja Mallik <rmallik@codeaurora.org>
parent 1e353927

Documentation/devicetree/bindings/media/video/msm-cam-ppi.txt

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+102 −0
Original line number Diff line number Diff line 
* Qualcomm Technologies, Inc. MSM camera PPI



=======================

Required Node Structure

=======================

The camera PPI node must be described in First level of device nodes. The

first level describe the overall PPI node structure.



======================================

First Level Node - PPI device

======================================



- compatible

  Usage: required

  Value type: <string>

  Definition: Should be "qcom,ppi-v1.0",

        "qcom,ppi-v1.1", "qcom,ppi-v1.2",

        "qcom,ppi-v2.0", "qcom,ppi".



- cell-index: ppi hardware core index

  Usage: required

  Value type: <u32>

  Definition: Should specify the Hardware index id.



- reg

  Usage: required

  Value type: <u32>

  Definition: offset and length of the register set

        for the device for the ppi operating in

        compatible mode.



- reg-names

  Usage: required

  Value type: <string>

  Definition: Should specify relevant names to each

        reg property defined.



- reg-cam-base

  Usage: required

  Value type: <string>

  Definition: offset of PPI in  camera hw block



- interrupts

  Usage: required

  Value type: <u32>

  Definition: Interrupt associated with PPI HW.



- interrupt-names

  Usage: required

  Value type: <string>

  Definition: Name of the interrupt.



- clock-names

  Usage: required

  Value type: <string>

  Definition: List of clock names required for PPI HW.



- clock-rates

  Usage: required

  Value type: <u32>

  Definition: List of clock rates in Hz for PPI HW.



- clock-cntl-level

  Usage: required

  Value type: <string>

  Definition: All different clock level node can support.



- clocks

  Usage: required

  Value type: <phandle>

  Definition: all clock phandle and source clocks.



- regulator-names

  Usage: required

  Value type: <string>

  Definition: name of the voltage regulators required for the device.



- gdscr-supply

  Usage: required

  Value type: <phandle>

  Definition: should contain gdsr regulator used for PPI clocks.



Example:

     qcom,ppi0@ace0000 {

     cell-index = <0>;

     compatible = "qcom,ppi170";

     reg-names = "ppi";

     reg = <0xace0000 0x200>;

     reg-cam-base = <0xe0000>;

     interrupt-names = "ppi";

     interrupts = <0 202 0>;

     regulator-names = "gdscr", "refgen";

     gdscr-supply = <&titan_top_gdsc>;

     clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

              <&clock_camcc CAM_CC_PPI0_CLK>,

              <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,

              <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;

     clock-names = "cphy_rx_clk_src", "ppi0_clk"

     clock-rates = <400000000 0 300000000 0>;

     clock-cntl-level = "turbo";

     status = "ok";

};

drivers/media/platform/msm/camera_v3/cam_core/cam_hw_mgr_intf.h

+12 −0
Original line number Diff line number Diff line
@@ -262,6 +262,16 @@ struct cam_hw_dump_pf_args { 
	bool                           *mem_found;

};



/**

 * struct cam_hw_reset_args -hw reset arguments

 *

 * @ctxt_to_hw_map:        HW context from the acquire

 *

 */

struct cam_hw_reset_args {

	void                           *ctxt_to_hw_map;

};



/* enum cam_hw_mgr_command - Hardware manager command type */

enum cam_hw_mgr_command {

	CAM_HW_MGR_CMD_INTERNAL,
@@ -313,6 +323,7 @@ struct cam_hw_cmd_args { 
 * @hw_open:                   Function pointer for HW init

 * @hw_close:                  Function pointer for HW deinit

 * @hw_flush:                  Function pointer for HW flush

 * @hw_reset:                  Function pointer for HW reset

 *

 */

struct cam_hw_mgr_intf {
@@ -333,6 +344,7 @@ struct cam_hw_mgr_intf { 
	int (*hw_open)(void *hw_priv, void *fw_download_args);

	int (*hw_close)(void *hw_priv, void *hw_close_args);

	int (*hw_flush)(void *hw_priv, void *hw_flush_args);

	int (*hw_reset)(void *hw_priv, void *hw_reset_args);

};



#endif /* _CAM_HW_MGR_INTF_H_ */

drivers/media/platform/msm/camera_v3/cam_cpas/cpas_top/cam_cpastop_hw.c

+8 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include "cam_cpas_soc.h"

#include "cpastop100.h"

#include "cpastop_v150_100.h"

#include "cpastop_v150_110.h"

#include "cpastop_v170_110.h"

#include "cpastop_v175_100.h"

#include "cpastop_v175_101.h"
@@ -117,6 +118,10 @@ static int cam_cpastop_get_hw_info(struct cam_hw_info *cpas_hw, 
			(hw_caps->cpas_version.minor == 0) &&

			(hw_caps->cpas_version.incr == 0))

			soc_info->hw_version = CAM_CPAS_TITAN_150_V100;

		else if ((hw_caps->cpas_version.major == 1) &&

			(hw_caps->cpas_version.minor == 1) &&

			(hw_caps->cpas_version.incr == 0))

			soc_info->hw_version = CAM_CPAS_TITAN_150_V110;

	}



	CAM_DBG(CAM_CPAS, "CPAS HW VERSION %x", soc_info->hw_version);
@@ -668,6 +673,9 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, 
	case CAM_CPAS_TITAN_150_V100:

		camnoc_info = &cam150_cpas100_camnoc_info;

		break;

	case CAM_CPAS_TITAN_150_V110:

		camnoc_info = &cam150_cpas110_camnoc_info;

		break;

	default:

		CAM_ERR(CAM_CPAS, "Camera Version not supported %d.%d.%d",

			hw_caps->camera_version.major,

drivers/media/platform/msm/camera_v3/cam_cpas/cpas_top/cpastop_v150_110.h

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Original line number Diff line number Diff line 
/* Copyright (c) 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _CPASTOP_V150_110_H_

#define _CPASTOP_V150_110_H_



#define TEST_IRQ_ENABLE 0



static struct cam_camnoc_irq_sbm cam_cpas_v150_110_irq_sbm = {

	.sbm_enable = {

		.access_type = CAM_REG_TYPE_READ_WRITE,

		.enable = true,

		.offset = 0x2040, /* SBM_FAULTINEN0_LOW */

		.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/

			0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */

			0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */

			0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */

			0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */

			0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */

			(TEST_IRQ_ENABLE ?

			0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */

			0x0),

	},

	.sbm_status = {

		.access_type = CAM_REG_TYPE_READ,

		.enable = true,

		.offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */

	},

	.sbm_clear = {

		.access_type = CAM_REG_TYPE_WRITE,

		.enable = true,

		.offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */

		.value = TEST_IRQ_ENABLE ? 0x6 : 0x2,

	}

};



static struct cam_camnoc_irq_err

	cam_cpas_v150_110_irq_err[] = {

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,

		.enable = true,

		.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR,

		.enable = true,

		.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR,

		.enable = true,

		.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,

		.enable = true,

		.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,

		.enable = true,

		.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x1190,

			/* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,

		.enable = true,

		.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */

			.value = 0x1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */

		},

		.err_clear = {

			.enable = false,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,

		.enable = false,

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,

		.enable = false,

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,

		.enable = TEST_IRQ_ENABLE ? true : false,

		.sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */

			.value = 0x5,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */

		},

		.err_clear = {

			.enable = false,

		},

	},

};



static struct cam_camnoc_specific

	cam_cpas_v150_110_camnoc_specific[] = {

	{

		.port_type = CAM_CAMNOC_CDM,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */

			.value = 0x22222222,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */

			.value = 0x22222222,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */

			.mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */

			.shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */

			.value = 0x2,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = false,

		},

	},

	{

		.port_type = CAM_CAMNOC_IFE02,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */

			.value = 0x66665433,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */

			.value = 0x66666666,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */

			/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */

			.mask = 0x70,

			/* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */

			.shift = 0x4,

			.value = 0x30,

		},

		.danger_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */

			.value = 0xFFFFFF00,

		},

		.safe_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */

			.value = 0x1,

		},

		.ubwc_ctl = {

			.enable = false,

		},

	},

	{

		.port_type = CAM_CAMNOC_IFE13,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */

			.value = 0x66665433,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */

			.value = 0x66666666,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */

			/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */

			.mask = 0x70,

			/* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */

			.shift = 0x4,

			.value = 0x30,

		},

		.danger_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */

			.value = 0xFFFFFF00,

		},

		.safe_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */

			.value = 0x1,

		},

		.ubwc_ctl = {

			.enable = false,

		},

	},

	{

		.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */

			.value = 0x33333333,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */

			.value = 0x33333333,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */

			/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */

			.mask = 0x7,

			/* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */

			.shift = 0x0,

			.value = 3,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */

			.value = 1,

		},

	},

	{

		.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */

			.value = 0x33333333,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */

			.value = 0x33333333,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 1,

			.offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */

			/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */

			.mask = 0x70,

			/* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */

			.shift = 0x4,

			.value = 0x30,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */

			.value = 0x5,

		},

	},

	{

		.port_type = CAM_CAMNOC_JPEG,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */

			.value = 0x22222222,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */

			.value = 0x22222222,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */

			.value = 0x22,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = false,

		},

	},

	{

		.port_type = CAM_CAMNOC_FD,

		.enable = false,

	},

	{

		.port_type = CAM_CAMNOC_ICP,

		.enable = true,

		.flag_out_set0_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_WRITE,

			.masked_value = 0,

			.offset = 0x2088,

			.value = 0x100000,

		},

	},

};



static struct cam_camnoc_err_logger_info cam150_cpas110_err_logger_offsets = {

	.mainctrl     =  0x2708, /* ERRLOGGER_MAINCTL_LOW */

	.errvld       =  0x2710, /* ERRLOGGER_ERRVLD_LOW */

	.errlog0_low  =  0x2720, /* ERRLOGGER_ERRLOG0_LOW */

	.errlog0_high =  0x2724, /* ERRLOGGER_ERRLOG0_HIGH */

	.errlog1_low  =  0x2728, /* ERRLOGGER_ERRLOG1_LOW */

	.errlog1_high =  0x272c, /* ERRLOGGER_ERRLOG1_HIGH */

	.errlog2_low  =  0x2730, /* ERRLOGGER_ERRLOG2_LOW */

	.errlog2_high =  0x2734, /* ERRLOGGER_ERRLOG2_HIGH */

	.errlog3_low  =  0x2738, /* ERRLOGGER_ERRLOG3_LOW */

	.errlog3_high =  0x273c, /* ERRLOGGER_ERRLOG3_HIGH */

};



static struct cam_cpas_hw_errata_wa_list cam150_cpas110_errata_wa_list = {

	.camnoc_flush_slave_pending_trans = {

		.enable = false,

		.data.reg_info = {

			.access_type = CAM_REG_TYPE_READ,

			.offset = 0x2100, /* SidebandManager_SenseIn0_Low */

			.mask = 0xE0000, /* Bits 17, 18, 19 */

			.value = 0, /* expected to be 0 */

		},

	},

};



static struct cam_camnoc_info cam150_cpas110_camnoc_info = {

	.specific = &cam_cpas_v150_110_camnoc_specific[0],

	.specific_size = sizeof(cam_cpas_v150_110_camnoc_specific) /

		sizeof(cam_cpas_v150_110_camnoc_specific[0]),

	.irq_sbm = &cam_cpas_v150_110_irq_sbm,

	.irq_err = &cam_cpas_v150_110_irq_err[0],

	.irq_err_size = sizeof(cam_cpas_v150_110_irq_err) /

		sizeof(cam_cpas_v150_110_irq_err[0]),

	.err_logger = &cam150_cpas110_err_logger_offsets,

	.errata_wa_list = &cam150_cpas110_errata_wa_list,

};



#endif /* _CPASTOP_V150_110_H_ */

drivers/media/platform/msm/camera_v3/cam_cpas/include/cam_cpas_api.h

+1 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ enum cam_cpas_reg_base { 
enum cam_cpas_hw_version {

	CAM_CPAS_TITAN_NONE = 0,

	CAM_CPAS_TITAN_150_V100 = 0x150100,

	CAM_CPAS_TITAN_150_V110 = 0x150110,

	CAM_CPAS_TITAN_170_V100 = 0x170100,

	CAM_CPAS_TITAN_170_V110 = 0x170110,

	CAM_CPAS_TITAN_170_V120 = 0x170120,