Merge "clk: qcom: gcc-sdm845: Update the PCIe pipe clock structures" (e3bc00dd) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/clk/qcom/clk-branch.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -92,7 +92,7 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling,
		} else if (br->halt_check == BRANCH_HALT_ENABLE \|\|
		br->halt_check == BRANCH_HALT \|\|
		(enabling && voted)) {
		int count = 200;
		int count = 500;

		while (count-- > 0) {
		if (check_halt(br, enabling))

+8 −6

Original line number	Diff line number	Diff line
		@@ -2027,14 +2027,15 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
		},
		};

		static struct clk_gate2 gcc_pcie_0_pipe_clk = {
		.udelay = 500,
		static struct clk_branch gcc_pcie_0_pipe_clk = {
		.halt_reg = 0x6b020,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x5200c,
		.enable_mask = BIT(4),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_0_pipe_clk",
		.ops = &clk_gate2_ops,
		.ops = &clk_branch2_ops,
		},
		},
		};
		@@ -2126,14 +2127,15 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
		},
		};

		static struct clk_gate2 gcc_pcie_1_pipe_clk = {
		.udelay = 500,
		static struct clk_branch gcc_pcie_1_pipe_clk = {
		.halt_reg = 0x8d020,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x52004,
		.enable_mask = BIT(30),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_1_pipe_clk",
		.ops = &clk_gate2_ops,
		.ops = &clk_branch2_ops,
		},
		},
		};