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Commit e3b454f7 authored by Heiko Stuebner's avatar Heiko Stuebner Committed by Kukjin Kim
Browse files

ARM: S3C2443: Move i2s clock definitions to common code 



S3C2416/S3C2450 use the same clocks for their i2s blocks
and can therefore reuse the existing ones.

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 7301794c

arch/arm/mach-s3c2443/clock.c

+0 −53
Original line number Diff line number Diff line
@@ -57,10 +57,6 @@ 


/* clock selections */



static struct clk clk_i2s_ext = {

	.name		= "i2s-ext",

};



/* armdiv

 *

 * this clock is sourced from msysclk and can have a number of
@@ -235,48 +231,6 @@ static struct clk clk_hsmmc = { 
	},

};



/* i2s_eplldiv

 *

 * This clock is the output from the I2S divisor of ESYSCLK, and is separate

 * from the mux that comes after it (cannot merge into one single clock)

*/



static struct clksrc_clk clk_i2s_eplldiv = {

	.clk	= {

		.name		= "i2s-eplldiv",

		.parent		= &clk_esysclk.clk,

	},

	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },

};



/* i2s-ref

 *

 * i2s bus reference clock, selectable from external, esysclk or epllref

 *

 * Note, this used to be two clocks, but was compressed into one.

*/



struct clk *clk_i2s_srclist[] = {

	[0] = &clk_i2s_eplldiv.clk,

	[1] = &clk_i2s_ext,

	[2] = &clk_epllref.clk,

	[3] = &clk_epllref.clk,

};



static struct clksrc_clk clk_i2s = {

	.clk	= {

		.name		= "i2s-if",

		.ctrlbit	= S3C2443_SCLKCON_I2SCLK,

		.enable		= s3c2443_clkcon_enable_s,



	},

	.sources = &(struct clksrc_sources) {

		.sources = clk_i2s_srclist,

		.nr_sources = ARRAY_SIZE(clk_i2s_srclist),

	},

	.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },

};



/* standard clock definitions */



static struct clk init_clocks_off[] = {
@@ -285,11 +239,6 @@ static struct clk init_clocks_off[] = { 
		.parent		= &clk_p,

		.enable		= s3c2443_clkcon_enable_p,

		.ctrlbit	= S3C2443_PCLKCON_SDI,

	}, {

		.name		= "iis",

		.parent		= &clk_p,

		.enable		= s3c2443_clkcon_enable_p,

		.ctrlbit	= S3C2443_PCLKCON_IIS,

	}, {

		.name		= "spi",

		.devname	= "s3c2410-spi.0",
@@ -312,8 +261,6 @@ static struct clk init_clocks[] = { 


static struct clksrc_clk *clksrcs[] __initdata = {

	&clk_arm,

	&clk_i2s_eplldiv,

	&clk_i2s,

	&clk_hsspi,

	&clk_hsmmc_div,

};

arch/arm/plat-s3c24xx/s3c2443-clock.c

+52 −0
Original line number Diff line number Diff line
@@ -205,9 +205,59 @@ static struct clksrc_clk clksrc_clks[] = { 
	},

};



static struct clk clk_i2s_ext = {

	.name		= "i2s-ext",

};



/* i2s_eplldiv

 *

 * This clock is the output from the I2S divisor of ESYSCLK, and is separate

 * from the mux that comes after it (cannot merge into one single clock)

*/



static struct clksrc_clk clk_i2s_eplldiv = {

	.clk	= {

		.name		= "i2s-eplldiv",

		.parent		= &clk_esysclk.clk,

	},

	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },

};



/* i2s-ref

 *

 * i2s bus reference clock, selectable from external, esysclk or epllref

 *

 * Note, this used to be two clocks, but was compressed into one.

*/



static struct clk *clk_i2s_srclist[] = {

	[0] = &clk_i2s_eplldiv.clk,

	[1] = &clk_i2s_ext,

	[2] = &clk_epllref.clk,

	[3] = &clk_epllref.clk,

};



static struct clksrc_clk clk_i2s = {

	.clk	= {

		.name		= "i2s-if",

		.ctrlbit	= S3C2443_SCLKCON_I2SCLK,

		.enable		= s3c2443_clkcon_enable_s,



	},

	.sources = &(struct clksrc_sources) {

		.sources = clk_i2s_srclist,

		.nr_sources = ARRAY_SIZE(clk_i2s_srclist),

	},

	.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },

};



static struct clk init_clocks_off[] = {

	{

		.name		= "iis",

		.parent		= &clk_p,

		.enable		= s3c2443_clkcon_enable_p,

		.ctrlbit	= S3C2443_PCLKCON_IIS,

	}, {

		.name		= "adc",

		.parent		= &clk_p,

		.enable		= s3c2443_clkcon_enable_p,
@@ -406,6 +456,8 @@ static struct clk *clks[] __initdata = { 
};



static struct clksrc_clk *clksrcs[] __initdata = {

	&clk_i2s_eplldiv,

	&clk_i2s,

	&clk_usb_bus_host,

	&clk_epllref,

	&clk_esysclk,