Loading arch/arm64/boot/dts/qcom/sdm670.dtsi +11 −4 Original line number Original line Diff line number Diff line Loading @@ -1034,11 +1034,18 @@ #clock-cells = <1>; #clock-cells = <1>; }; }; clock_cpucc: qcom,cpucc { clock_cpucc: qcom,cpucc@0x17d41000 { compatible = "qcom,dummycc"; compatible = "qcom,clk-cpu-osm-sdm670"; clock-output-names = "cpucc_clocks"; reg = <0x17d41000 0x1400>, <0x17d43000 0x1400>, <0x17d45800 0x1400>; reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base"; l3-devs = <&l3_cpu0 &l3_cpu6>; clock-names = "xo_ao"; clocks = <&clock_rpmh RPMH_CXO_CLK_A>; #clock-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; }; }; clock_aop: qcom,aopclk { clock_aop: qcom,aopclk { Loading Loading
arch/arm64/boot/dts/qcom/sdm670.dtsi +11 −4 Original line number Original line Diff line number Diff line Loading @@ -1034,11 +1034,18 @@ #clock-cells = <1>; #clock-cells = <1>; }; }; clock_cpucc: qcom,cpucc { clock_cpucc: qcom,cpucc@0x17d41000 { compatible = "qcom,dummycc"; compatible = "qcom,clk-cpu-osm-sdm670"; clock-output-names = "cpucc_clocks"; reg = <0x17d41000 0x1400>, <0x17d43000 0x1400>, <0x17d45800 0x1400>; reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base"; l3-devs = <&l3_cpu0 &l3_cpu6>; clock-names = "xo_ao"; clocks = <&clock_rpmh RPMH_CXO_CLK_A>; #clock-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; }; }; clock_aop: qcom,aopclk { clock_aop: qcom,aopclk { Loading