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Commit e3842f3c authored by Gopikrishnaiah Anandan's avatar Gopikrishnaiah Anandan Committed by Narendra Muppalla
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drm/msm/sde: update catalog for post processing 



Update catalog for post processing features.

Change-Id: I6b43ee213e504780f8e6bacee0ca7e370a381772
Signed-off-by: default avatarGopikrishnaiah Anandan <agopik@codeaurora.org>
parent 17e908b5

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+26 −11
Original line number Diff line number Diff line
@@ -46,6 +46,11 @@ 


#define CRTC_DUAL_MIXERS	2



#define SDE_COLOR_PROCESS_VER(MAJOR, MINOR) \

		((((MAJOR) & 0xFFFF) << 16) | (((MINOR) & 0xFFFF)))

#define SDE_COLOR_PROCESS_MAJOR(version) (((version) & 0xFFFF0000) >> 16)

#define SDE_COLOR_PROCESS_MINOR(version) ((version) & 0xFFFF)



/**

 * MDP TOP BLOCK features

 * @SDE_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe
@@ -75,8 +80,8 @@ enum { 
 * @SDE_SSPP_SCALER_QSEED3,  QSEED3 alogorithm support

 * @SDE_SSPP_SCALER_RGB,     RGB Scaler, supported by RGB pipes

 * @SDE_SSPP_CSC,            Support of Color space converion

 * @SDE_SSPP_PA_V1,          Common op-mode register for PA blocks

 * @SDE_SSPP_HIST_V1         Histogram programming method V1

 * @SDE_SSPP_HSIC,           Global HSIC control

 * @SDE_SSPP_MEMCOLOR        Memory Color Support

 * @SDE_SSPP_IGC,            Inverse gamma correction

 * @SDE_SSPP_PCC,            Color correction support

 * @SDE_SSPP_CURSOR,         SSPP can be used as a cursor layer
@@ -89,8 +94,8 @@ enum { 
	SDE_SSPP_SCALER_QSEED3,

	SDE_SSPP_SCALER_RGB,

	SDE_SSPP_CSC,

	SDE_SSPP_PA_V1, /* Common op-mode register for PA blocks */

	SDE_SSPP_HIST_V1,

	SDE_SSPP_HSIC,

	SDE_SSPP_MEMCOLOR,

	SDE_SSPP_IGC,

	SDE_SSPP_PCC,

	SDE_SSPP_CURSOR,
@@ -117,7 +122,9 @@ enum { 
 * @SDE_DSPP_IGC             DSPP Inverse gamma correction block

 * @SDE_DSPP_PCC             Panel color correction block

 * @SDE_DSPP_GC              Gamma correction block

 * @SDE_DSPP_PA              Picture adjustment block

 * @SDE_DSPP_HSIC            Global HSIC block

 * @SDE_DSPP_MEMCOLOR        Memory Color block

 * @SDE_DSPP_SIXZONE         Six zone block

 * @SDE_DSPP_GAMUT           Gamut bloc

 * @SDE_DSPP_DITHER          Dither block

 * @SDE_DSPP_HIST            Histogram bloc
@@ -127,7 +134,9 @@ enum { 
	SDE_DSPP_IGC = 0x1,

	SDE_DSPP_PCC,

	SDE_DSPP_GC,

	SDE_DSPP_PA,

	SDE_DSPP_HSIC,

	SDE_DSPP_MEMCOLOR,

	SDE_DSPP_SIXZONE,

	SDE_DSPP_GAMUT,

	SDE_DSPP_DITHER,

	SDE_DSPP_HIST,
@@ -290,9 +299,10 @@ struct sde_format_extended { 
 * @src_blk:

 * @scaler_blk:

 * @csc_blk:

 * @pa_blk:

 * @hist_lut:

 * @hsic:

 * @memcolor:

 * @pcc_blk:

 * @igc_blk:

 * @format_list: Pointer to list of supported formats

 */

struct sde_sspp_sub_blks {
@@ -314,9 +324,10 @@ struct sde_sspp_sub_blks { 
	struct sde_src_blk src_blk;

	struct sde_scaler_blk scaler_blk;

	struct sde_pp_blk csc_blk;

	struct sde_pp_blk pa_blk;

	struct sde_pp_blk hist_lut;

	struct sde_pp_blk hsic;

	struct sde_pp_blk memcolor;

	struct sde_pp_blk pcc_blk;

	struct sde_pp_blk igc_blk;



	const struct sde_format_extended *format_list;

};
@@ -326,18 +337,22 @@ struct sde_sspp_sub_blks { 
 * @maxwidth:               Max pixel width supported by this mixer

 * @maxblendstages:         Max number of blend-stages supported

 * @blendstage_base:        Blend-stage register base offset

 * @gc: gamma correction block

 */

struct sde_lm_sub_blks {

	u32 maxwidth;

	u32 maxblendstages;

	u32 blendstage_base[MAX_BLOCKS];

	struct sde_pp_blk gc;

};



struct sde_dspp_sub_blks {

	struct sde_pp_blk igc;

	struct sde_pp_blk pcc;

	struct sde_pp_blk gc;

	struct sde_pp_blk pa;

	struct sde_pp_blk hsic;

	struct sde_pp_blk memcolor;

	struct sde_pp_blk sixzone;

	struct sde_pp_blk gamut;

	struct sde_pp_blk dither;

	struct sde_pp_blk hist;

drivers/gpu/drm/msm/sde/sde_hw_catalog_8996.c

+45 −38
Original line number Diff line number Diff line 
/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -17,9 +17,9 @@ 
/* VIG layer capability */

#define VIG_17X_MASK \

	(BIT(SDE_SSPP_SRC) | BIT(SDE_SSPP_SCALER_QSEED2) |\

	BIT(SDE_SSPP_CSC) | BIT(SDE_SSPP_PA_V1) |\

	BIT(SDE_SSPP_HIST_V1) | BIT(SDE_SSPP_PCC) |\

	BIT(SDE_SSPP_IGC) | BIT(SDE_SSPP_QOS))

	BIT(SDE_SSPP_CSC) | BIT(SDE_SSPP_HSIC) |\

	BIT(SDE_SSPP_PCC) | BIT(SDE_SSPP_IGC) |\

	BIT(SDE_SSPP_MEMCOLOR) | BIT(SDE_SSPP_QOS))



/* RGB layer capability */

#define RGB_17X_MASK \
@@ -28,8 +28,8 @@ 


/* DMA layer capability */

#define DMA_17X_MASK \

	(BIT(SDE_SSPP_SRC) | BIT(SDE_SSPP_PA_V1) |\

	BIT(SDE_SSPP_PCC) | BIT(SDE_SSPP_IGC) | BIT(SDE_SSPP_QOS))

	(BIT(SDE_SSPP_SRC) | BIT(SDE_SSPP_PCC) | BIT(SDE_SSPP_IGC) |\

	BIT(SDE_SSPP_QOS))



/* Cursor layer capability */

#define CURSOR_17X_MASK  (BIT(SDE_SSPP_SRC) | BIT(SDE_SSPP_CURSOR))
@@ -39,8 +39,9 @@ 


#define DSPP_17X_MASK \

	(BIT(SDE_DSPP_IGC) | BIT(SDE_DSPP_PCC) |\

	BIT(SDE_DSPP_GC) | BIT(SDE_DSPP_PA) | BIT(SDE_DSPP_GAMUT) |\

	BIT(SDE_DSPP_DITHER) | BIT(SDE_DSPP_HIST))

	BIT(SDE_DSPP_GC) | BIT(SDE_DSPP_HSIC) | BIT(SDE_DSPP_GAMUT) |\

	BIT(SDE_DSPP_DITHER) | BIT(SDE_DSPP_HIST) | BIT(SDE_DSPP_MEMCOLOR) |\

	BIT(SDE_DSPP_SIXZONE))



#define PINGPONG_17X_MASK \

	(BIT(SDE_PINGPONG_TE) | BIT(SDE_PINGPONG_DSC))
@@ -254,13 +255,15 @@ static inline int set_cfg_1xx_init(struct sde_mdss_cfg *cfg) 
			.base = 0x200, .len = 0x70,},

		.csc_blk = {.id = SDE_SSPP_CSC,

			.base = 0x320, .len = 0x44,},

		.pa_blk = {.id = SDE_SSPP_PA_V1,

			.base = 0x200, .len = 0x0,},

		.hist_lut = {.id = SDE_SSPP_HIST_V1,

			.base = 0xA00, .len = 0x400,},

		.pcc_blk = {.id = SDE_SSPP_PCC,

			.base = 0x1780, .len = 0x64,},

		.format_list = plane_formats_yuv,

		.igc_blk = {.id = SDE_SSPP_IGC, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.pcc_blk = {.id = SDE_SSPP_PCC, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.hsic = {.id = SDE_SSPP_HSIC, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.memcolor = {.id = SDE_SSPP_MEMCOLOR, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

	};



	static const struct sde_sspp_sub_blks layer = {
@@ -284,13 +287,11 @@ static inline int set_cfg_1xx_init(struct sde_mdss_cfg *cfg) 
			.base = 0x200, .len = 0x70,},

		.csc_blk = {.id = SDE_SSPP_CSC,

			.base = 0x320, .len = 0x44,},

		.pa_blk = {.id = SDE_SSPP_PA_V1,

			.base = 0x200, .len = 0x0,},

		.hist_lut = {.id = SDE_SSPP_HIST_V1,

			.base = 0xA00, .len = 0x400,},

		.pcc_blk = {.id = SDE_SSPP_PCC,

			.base = 0x1780, .len = 0x64,},

		.format_list = plane_formats,

		.igc_blk = {.id = SDE_SSPP_IGC, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.pcc_blk = {.id = SDE_SSPP_PCC, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

	};



	static const struct sde_sspp_sub_blks dma = {
@@ -311,10 +312,11 @@ static inline int set_cfg_1xx_init(struct sde_mdss_cfg *cfg) 
		.src_blk = {.id = SDE_SSPP_SRC, .base = 0x00, .len = 0x150,},

		.scaler_blk = {.id = 0, .base = 0x00, .len = 0x0,},

		.csc_blk = {.id = 0, .base = 0x00, .len = 0x0,},

		.pa_blk = {.id = 0, .base = 0x200, .len = 0x0,},

		.hist_lut = {.id = 0, .base = 0xA00, .len = 0x0,},

		.pcc_blk = {.id = SDE_SSPP_PCC, .base = 0x01780, .len = 0x64,},

		.format_list = plane_formats,

		.igc_blk = {.id = SDE_SSPP_IGC, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.pcc_blk = {.id = SDE_SSPP_PCC, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

	};



	static const struct sde_sspp_sub_blks cursor = {
@@ -325,9 +327,6 @@ static inline int set_cfg_1xx_init(struct sde_mdss_cfg *cfg) 
		.src_blk = {.id = SDE_SSPP_SRC, .base = 0x00, .len = 0x150,},

		.scaler_blk = {.id = 0, .base = 0x00, .len = 0x0,},

		.csc_blk = {.id = 0, .base = 0x00, .len = 0x0,},

		.pa_blk = {.id = 0, .base = 0x00, .len = 0x0,},

		.hist_lut = {.id = 0, .base = 0x00, .len = 0x0,},

		.pcc_blk = {.id = 0, .base = 0x00, .len = 0x0,},

		.format_list = plane_formats,

	};
@@ -336,23 +335,31 @@ static inline int set_cfg_1xx_init(struct sde_mdss_cfg *cfg) 
		.maxwidth = 2560,

		.maxblendstages = 7, /* excluding base layer */

		.blendstage_base = { /* offsets relative to mixer base */

			0x20, 0x50, 0x80, 0xB0, 0x230, 0x260, 0x290 }

			0x20, 0x50, 0x80, 0xB0, 0x230, 0x260, 0x290 },

		.gc = {.id = SDE_DSPP_GC, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

	};



	/* DSPP capability */

	static const struct sde_dspp_sub_blks dspp = {

			.igc = {.id = SDE_DSPP_GC, .base = 0x17c0, .len = 0x0,

				.version = 0x1},

		.pcc = {.id = SDE_DSPP_PCC, .base = 0x00, .len = 0x0,

			.version = 0x1},

		.gamut = {.id = SDE_DSPP_GAMUT, .base = 0x01600, .len = 0x0,

			.version = 0x1},

		.dither = {.id = SDE_DSPP_DITHER, .base = 0x00, .len = 0x0,

			.version = 0x1},

		.pa = {.id = SDE_DSPP_PA, .base = 0x00, .len = 0x0,

			.version = 0x1},

		.igc = {.id = SDE_DSPP_IGC, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.pcc = {.id = SDE_DSPP_PCC, .base = 0x0, .len = 0x7,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.gamut = {.id = SDE_DSPP_GAMUT, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.dither = {.id = SDE_DSPP_DITHER, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.hsic = {.id = SDE_DSPP_HSIC, .base = 0x00, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.memcolor = {.id = SDE_DSPP_MEMCOLOR, .base = 0x00, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.sixzone = {.id = SDE_DSPP_SIXZONE, .base = 0x00, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.hist = {.id = SDE_DSPP_HIST, .base = 0x00, .len = 0x0,

			.version = 0x1},

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

		.gc = {.id = SDE_DSPP_GC, .base = 0x0, .len = 0x0,

			.version = SDE_COLOR_PROCESS_VER(0x1, 0x0)},

	};



	/* PINGPONG capability */

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+8 −10
Original line number Diff line number Diff line 
/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -125,15 +125,15 @@ static inline int _sspp_subblk_offset(struct sde_hw_pipe *ctx, 
	case SDE_SSPP_CSC:

		*idx = sblk->csc_blk.base;

		break;

	case SDE_SSPP_PA_V1:

		*idx = sblk->pa_blk.base;

		break;

	case SDE_SSPP_HIST_V1:

		*idx = sblk->hist_lut.base;

	case SDE_SSPP_HSIC:

		*idx = sblk->hsic.base;

		break;

	case SDE_SSPP_PCC:

		*idx = sblk->pcc_blk.base;

		break;

	case SDE_SSPP_MEMCOLOR:

		*idx = sblk->memcolor.base;

		break;

	default:

		rc = -EINVAL;

	}
@@ -148,8 +148,7 @@ static void _sspp_setup_opmode(struct sde_hw_pipe *ctx, 
	u32 opmode;



	if (!_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) &&

			(test_bit(SDE_SSPP_CSC, &ctx->cap->features) ||

			 test_bit(SDE_SSPP_PA_V1, &ctx->cap->features))) {

			test_bit(SDE_SSPP_CSC, &ctx->cap->features)) {

		opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx);



		if (en)
@@ -526,10 +525,9 @@ static void _setup_layer_ops(struct sde_hw_sspp_ops *ops, 
	if (test_bit(SDE_SSPP_CSC, &features))

		ops->setup_csc = sde_hw_sspp_setup_csc;



	if (test_bit(SDE_SSPP_PA_V1, &features)) {

	if (test_bit(SDE_SSPP_SCALER_QSEED2, &features))

		ops->setup_sharpening = sde_hw_sspp_setup_sharpening;

}

}



static struct sde_sspp_cfg *_sspp_offset(enum sde_sspp sspp,

		void __iomem *addr,