Commit e3230494 authored Nov 25, 2016 by Martin Blumenstingl Committed by David S. Miller Nov 28, 2016

net: phy: realtek: fix enabling of the TX-delay for RTL8211F



The old logic always enabled the TX-delay when the phy-mode was set to
PHY_INTERFACE_MODE_RGMII. There are dedicated phy-modes which tell the
PHY driver to enable the RX and/or TX delays:
- PHY_INTERFACE_MODE_RGMII should disable the RX and TX delay in the
  PHY (if required, the MAC should add the delays in this case)
- PHY_INTERFACE_MODE_RGMII_ID should enable RX and TX delay in the PHY
- PHY_INTERFACE_MODE_RGMII_TXID should enable the TX delay in the PHY
- PHY_INTERFACE_MODE_RGMII_RXID should enable the RX delay in the PHY
  (currently not supported by RTL8211F)

With this patch we enable the TX delay for PHY_INTERFACE_MODE_RGMII_ID
and PHY_INTERFACE_MODE_RGMII_TXID.
Additionally we now explicity disable the TX-delay, which seems to be
enabled automatically after a hard-reset of the PHY (by triggering it's
reset pin) to get a consistent state (as defined by the phy-mode).

This fixes a compatibility problem with some SoCs where the TX-delay was
also added by the MAC. With the TX-delay being applied twice the TX
clock was off and TX traffic was broken or very slow (<10Mbit/s) on
1000Mbit/s links.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent e5f3a4a5

drivers/net/phy/realtek.c

+12 −8

Original line number	Diff line number	Diff line
		@@ -102,15 +102,19 @@ static int rtl8211f_config_init(struct phy_device *phydev)
		if (ret < 0)
		return ret;

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
		/* enable TXDLY */
		phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
		reg = phy_read(phydev, 0x11);

		/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID \|\|
		phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
		reg \|= RTL8211F_TX_DELAY;
		else
		reg &= ~RTL8211F_TX_DELAY;

		phy_write(phydev, 0x11, reg);
		/* restore to default page 0 */
		phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
		}

		return 0;
		}