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Commit e3090387 authored by Vinod Koul's avatar Vinod Koul Committed by Mark Brown
Browse files

ASoC: Intel: Skylake: Add code loader DMA registers 



Skylake has a DMA controller for loading DSP code and modules to memory.
Add the register defines for this DMA

Signed-off-by: default avatarSubhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: default avatarJeeja KP <jeeja.kp@intel.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent b6626802

sound/soc/intel/skylake/skl-sst-cldma.h

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+191 −0
Original line number Diff line number Diff line 
/*

 * Intel Code Loader DMA support

 *

 * Copyright (C) 2015, Intel Corporation.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as version 2, as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * General Public License for more details.

 */



#ifndef SKL_SST_CLDMA_H_

#define SKL_SST_CLDMA_H_



#define FW_CL_STREAM_NUMBER		0x1



#define DMA_ADDRESS_128_BITS_ALIGNMENT	7

#define BDL_ALIGN(x)			(x >> DMA_ADDRESS_128_BITS_ALIGNMENT)



#define SKL_ADSPIC_CL_DMA			0x2

#define SKL_ADSPIS_CL_DMA			0x2

#define SKL_CL_DMA_SD_INT_DESC_ERR		0x10 /* Descriptor error interrupt */

#define SKL_CL_DMA_SD_INT_FIFO_ERR		0x08 /* FIFO error interrupt */

#define SKL_CL_DMA_SD_INT_COMPLETE		0x04 /* Buffer completion interrupt */



/* Intel HD Audio Code Loader DMA Registers */



#define HDA_ADSP_LOADER_BASE		0x80



/* Stream Registers */

#define SKL_ADSP_REG_CL_SD_CTL			(HDA_ADSP_LOADER_BASE + 0x00)

#define SKL_ADSP_REG_CL_SD_STS			(HDA_ADSP_LOADER_BASE + 0x03)

#define SKL_ADSP_REG_CL_SD_LPIB			(HDA_ADSP_LOADER_BASE + 0x04)

#define SKL_ADSP_REG_CL_SD_CBL			(HDA_ADSP_LOADER_BASE + 0x08)

#define SKL_ADSP_REG_CL_SD_LVI			(HDA_ADSP_LOADER_BASE + 0x0c)

#define SKL_ADSP_REG_CL_SD_FIFOW		(HDA_ADSP_LOADER_BASE + 0x0e)

#define SKL_ADSP_REG_CL_SD_FIFOSIZE		(HDA_ADSP_LOADER_BASE + 0x10)

#define SKL_ADSP_REG_CL_SD_FORMAT		(HDA_ADSP_LOADER_BASE + 0x12)

#define SKL_ADSP_REG_CL_SD_FIFOL		(HDA_ADSP_LOADER_BASE + 0x14)

#define SKL_ADSP_REG_CL_SD_BDLPL		(HDA_ADSP_LOADER_BASE + 0x18)

#define SKL_ADSP_REG_CL_SD_BDLPU		(HDA_ADSP_LOADER_BASE + 0x1c)



/* CL: Software Position Based FIFO Capability Registers */

#define SKL_ADSP_REG_CL_SPBFIFO			(HDA_ADSP_LOADER_BASE + 0x20)

#define SKL_ADSP_REG_CL_SPBFIFO_SPBFCH		(SKL_ADSP_REG_CL_SPBFIFO + 0x0)

#define SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL	(SKL_ADSP_REG_CL_SPBFIFO + 0x4)

#define SKL_ADSP_REG_CL_SPBFIFO_SPIB		(SKL_ADSP_REG_CL_SPBFIFO + 0x8)

#define SKL_ADSP_REG_CL_SPBFIFO_MAXFIFOS	(SKL_ADSP_REG_CL_SPBFIFO + 0xc)



/* CL: Stream Descriptor x Control */



/* Stream Reset */

#define CL_SD_CTL_SRST_SHIFT		0

#define CL_SD_CTL_SRST_MASK		(1 << CL_SD_CTL_SRST_SHIFT)

#define CL_SD_CTL_SRST(x)		\

			((x << CL_SD_CTL_SRST_SHIFT) & CL_SD_CTL_SRST_MASK)



/* Stream Run */

#define CL_SD_CTL_RUN_SHIFT		1

#define CL_SD_CTL_RUN_MASK		(1 << CL_SD_CTL_RUN_SHIFT)

#define CL_SD_CTL_RUN(x)		\

			((x << CL_SD_CTL_RUN_SHIFT) & CL_SD_CTL_RUN_MASK)



/* Interrupt On Completion Enable */

#define CL_SD_CTL_IOCE_SHIFT		2

#define CL_SD_CTL_IOCE_MASK		(1 << CL_SD_CTL_IOCE_SHIFT)

#define CL_SD_CTL_IOCE(x)		\

			((x << CL_SD_CTL_IOCE_SHIFT) & CL_SD_CTL_IOCE_MASK)



/* FIFO Error Interrupt Enable */

#define CL_SD_CTL_FEIE_SHIFT		3

#define CL_SD_CTL_FEIE_MASK		(1 << CL_SD_CTL_FEIE_SHIFT)

#define CL_SD_CTL_FEIE(x)		\

			((x << CL_SD_CTL_FEIE_SHIFT) & CL_SD_CTL_FEIE_MASK)



/* Descriptor Error Interrupt Enable */

#define CL_SD_CTL_DEIE_SHIFT		4

#define CL_SD_CTL_DEIE_MASK		(1 << CL_SD_CTL_DEIE_SHIFT)

#define CL_SD_CTL_DEIE(x)		\

			((x << CL_SD_CTL_DEIE_SHIFT) & CL_SD_CTL_DEIE_MASK)



/* FIFO Limit Change */

#define CL_SD_CTL_FIFOLC_SHIFT		5

#define CL_SD_CTL_FIFOLC_MASK		(1 << CL_SD_CTL_FIFOLC_SHIFT)

#define CL_SD_CTL_FIFOLC(x)		\

			((x << CL_SD_CTL_FIFOLC_SHIFT) & CL_SD_CTL_FIFOLC_MASK)



/* Stripe Control */

#define CL_SD_CTL_STRIPE_SHIFT		16

#define CL_SD_CTL_STRIPE_MASK		(0x3 << CL_SD_CTL_STRIPE_SHIFT)

#define CL_SD_CTL_STRIPE(x)		\

			((x << CL_SD_CTL_STRIPE_SHIFT) & CL_SD_CTL_STRIPE_MASK)



/* Traffic Priority */

#define CL_SD_CTL_TP_SHIFT		18

#define CL_SD_CTL_TP_MASK		(1 << CL_SD_CTL_TP_SHIFT)

#define CL_SD_CTL_TP(x)			\

			((x << CL_SD_CTL_TP_SHIFT) & CL_SD_CTL_TP_MASK)



/* Bidirectional Direction Control */

#define CL_SD_CTL_DIR_SHIFT		19

#define CL_SD_CTL_DIR_MASK		(1 << CL_SD_CTL_DIR_SHIFT)

#define CL_SD_CTL_DIR(x)		\

			((x << CL_SD_CTL_DIR_SHIFT) & CL_SD_CTL_DIR_MASK)



/* Stream Number */

#define CL_SD_CTL_STRM_SHIFT		20

#define CL_SD_CTL_STRM_MASK		(0xf << CL_SD_CTL_STRM_SHIFT)

#define CL_SD_CTL_STRM(x)		\

			((x << CL_SD_CTL_STRM_SHIFT) & CL_SD_CTL_STRM_MASK)



/* CL: Stream Descriptor x Status */



/* Buffer Completion Interrupt Status */

#define CL_SD_STS_BCIS(x)		CL_SD_CTL_IOCE(x)



/* FIFO Error */

#define CL_SD_STS_FIFOE(x)		CL_SD_CTL_FEIE(x)



/* Descriptor Error */

#define CL_SD_STS_DESE(x)		CL_SD_CTL_DEIE(x)



/* FIFO Ready */

#define CL_SD_STS_FIFORDY(x)	CL_SD_CTL_FIFOLC(x)





/* CL: Stream Descriptor x Last Valid Index */

#define CL_SD_LVI_SHIFT			0

#define CL_SD_LVI_MASK			(0xff << CL_SD_LVI_SHIFT)

#define CL_SD_LVI(x)			((x << CL_SD_LVI_SHIFT) & CL_SD_LVI_MASK)



/* CL: Stream Descriptor x FIFO Eviction Watermark */

#define CL_SD_FIFOW_SHIFT		0

#define CL_SD_FIFOW_MASK		(0x7 << CL_SD_FIFOW_SHIFT)

#define CL_SD_FIFOW(x)			\

			((x << CL_SD_FIFOW_SHIFT) & CL_SD_FIFOW_MASK)



/* CL: Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address */



/* Protect Bits */

#define CL_SD_BDLPLBA_PROT_SHIFT	0

#define CL_SD_BDLPLBA_PROT_MASK		(1 << CL_SD_BDLPLBA_PROT_SHIFT)

#define CL_SD_BDLPLBA_PROT(x)		\

		((x << CL_SD_BDLPLBA_PROT_SHIFT) & CL_SD_BDLPLBA_PROT_MASK)



/* Buffer Descriptor List Lower Base Address */

#define CL_SD_BDLPLBA_SHIFT		7

#define CL_SD_BDLPLBA_MASK		(0x1ffffff << CL_SD_BDLPLBA_SHIFT)

#define CL_SD_BDLPLBA(x)		\

	((BDL_ALIGN(lower_32_bits(x)) << CL_SD_BDLPLBA_SHIFT) & CL_SD_BDLPLBA_MASK)



/* Buffer Descriptor List Upper Base Address */

#define CL_SD_BDLPUBA_SHIFT		0

#define CL_SD_BDLPUBA_MASK		(0xffffffff << CL_SD_BDLPUBA_SHIFT)

#define CL_SD_BDLPUBA(x)		\

		((upper_32_bits(x) << CL_SD_BDLPUBA_SHIFT) & CL_SD_BDLPUBA_MASK)



/*

 * Code Loader - Software Position Based FIFO

 * Capability Registers x Software Position Based FIFO Header

 */



/* Next Capability Pointer */

#define CL_SPBFIFO_SPBFCH_PTR_SHIFT	0

#define CL_SPBFIFO_SPBFCH_PTR_MASK	(0xff << CL_SPBFIFO_SPBFCH_PTR_SHIFT)

#define CL_SPBFIFO_SPBFCH_PTR(x)	\

		((x << CL_SPBFIFO_SPBFCH_PTR_SHIFT) & CL_SPBFIFO_SPBFCH_PTR_MASK)



/* Capability Identifier */

#define CL_SPBFIFO_SPBFCH_ID_SHIFT	16

#define CL_SPBFIFO_SPBFCH_ID_MASK	(0xfff << CL_SPBFIFO_SPBFCH_ID_SHIFT)

#define CL_SPBFIFO_SPBFCH_ID(x)		\

		((x << CL_SPBFIFO_SPBFCH_ID_SHIFT) & CL_SPBFIFO_SPBFCH_ID_MASK)



/* Capability Version */

#define CL_SPBFIFO_SPBFCH_VER_SHIFT	28

#define CL_SPBFIFO_SPBFCH_VER_MASK	(0xf << CL_SPBFIFO_SPBFCH_VER_SHIFT)

#define CL_SPBFIFO_SPBFCH_VER(x)	\

	((x << CL_SPBFIFO_SPBFCH_VER_SHIFT) & CL_SPBFIFO_SPBFCH_VER_MASK)



/* Software Position in Buffer Enable */

#define CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT	0

#define CL_SPBFIFO_SPBFCCTL_SPIBE_MASK	(1 << CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT)

#define CL_SPBFIFO_SPBFCCTL_SPIBE(x)	\

	((x << CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT) & CL_SPBFIFO_SPBFCCTL_SPIBE_MASK)



#endif /* SKL_SST_CLDMA_H_ */