Merge "msm: pcie: add support for switch latency" (e2a1a321) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/pci/msm_pcie.txt

+4 −0

Original line number	Diff line number	Diff line
		@@ -95,6 +95,9 @@ Optional Properties:
		and assign for each endpoint.
		- qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become
		stable after power on, before de-assert the PERST to the endpoint.
		- qcom,switch-latency: The time (unit: ms) to wait for the PCIe endpoint's link
		training with switch downstream port after the link between switch upstream
		port and RC is up.
		- qcom,wr-halt-size: With base 2, this exponent determines the size of the
		data that PCIe core will halt on for each write transaction.
		- qcom,slv-addr-space-size: The memory space size of PCIe Root Complex.
		@@ -268,6 +271,7 @@ Example:
		qcom,smmu-exist;
		qcom,smmu-sid-base = <0x1480>;
		qcom,ep-latency = <100>;
		qcom,switch-latency = <100>;
		qcom,wr-halt-size = <0xa>; /* 1KB */
		qcom,slv-addr-space-size = <0x1000000>; /* 16MB */
		qcom,cpl-timeout = <0x2>;

drivers/pci/host/pci-msm.c

+28 −0

Original line number	Diff line number	Diff line
		@@ -140,6 +140,7 @@

		#define PERST_PROPAGATION_DELAY_US_MIN 1000
		#define PERST_PROPAGATION_DELAY_US_MAX 1005
		#define SWITCH_DELAY_MAX 20
		#define REFCLK_STABILIZATION_DELAY_US_MIN 1000
		#define REFCLK_STABILIZATION_DELAY_US_MAX 1005
		#define LINK_UP_TIMEOUT_US_MIN 5000
		@@ -492,6 +493,7 @@ struct msm_pcie_dev_t {
		uint32_t max_link_speed;
		bool ext_ref_clk;
		uint32_t ep_latency;
		uint32_t switch_latency;
		uint32_t wr_halt_size;
		uint32_t slv_addr_space_size;
		uint32_t cpl_timeout;
		@@ -1112,6 +1114,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev)
		dev->n_fts);
		PCIE_DBG_FS(dev, "ep_latency: %dms\n",
		dev->ep_latency);
		PCIE_DBG_FS(dev, "switch_latency: %dms\n",
		dev->switch_latency);
		PCIE_DBG_FS(dev, "wr_halt_size: 0x%x\n",
		dev->wr_halt_size);
		PCIE_DBG_FS(dev, "slv_addr_space_size: 0x%x\n",
		@@ -3821,6 +3825,16 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
		goto link_fail;
		}

		if (dev->switch_latency) {
		PCIE_DBG(dev, "switch_latency: %dms\n",
		dev->switch_latency);
		if (dev->switch_latency <= SWITCH_DELAY_MAX)
		usleep_range(dev->switch_latency * 1000,
		dev->switch_latency * 1000);
		else
		msleep(dev->switch_latency);
		}

		msm_pcie_config_controller(dev);

		if (!dev->msi_gicm_addr)
		@@ -5366,6 +5380,20 @@ static int msm_pcie_probe(struct platform_device *pdev)
		PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: ep-latency: 0x%x.\n",
		rc_idx, msm_pcie_dev[rc_idx].ep_latency);

		msm_pcie_dev[rc_idx].switch_latency = 0;
		ret = of_property_read_u32((&pdev->dev)->of_node,
		"qcom,switch-latency",
		&msm_pcie_dev[rc_idx].switch_latency);

		if (ret)
		PCIE_DBG(&msm_pcie_dev[rc_idx],
		"RC%d: switch-latency does not exist.\n",
		rc_idx);
		else
		PCIE_DBG(&msm_pcie_dev[rc_idx],
		"RC%d: switch-latency: 0x%x.\n",
		rc_idx, msm_pcie_dev[rc_idx].switch_latency);

		msm_pcie_dev[rc_idx].wr_halt_size = 0;
		ret = of_property_read_u32(pdev->dev.of_node,
		"qcom,wr-halt-size",