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Commit e1cd8454 authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
Browse files

ARM: EXYNOS: Modify platform data for pl330 driver 



With the 'struct dma_pl330_peri' removed, the platfrom data for dma
driver can be simplified to a simple list of peripheral request ids.

Cc: Jassi Brar <jassisinghbrar@gmail.com>
Acked-by: default avatarBoojin Kim <boojin.kim@samsung.com>
Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Acked-by: default avatarGrant Likely <grant.likely@secretlab.ca>
Acked-by: default avatarVinod Koul <vinod.koul@intel.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent cd072515

arch/arm/mach-exynos/dma.c

+64 −161
Original line number Diff line number Diff line
@@ -35,95 +35,42 @@ 


static u64 dma_dmamask = DMA_BIT_MASK(32);



struct dma_pl330_peri pdma0_peri[28] = {

	{

		.peri_id = (u8)DMACH_PCM0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_PCM0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_PCM2_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_PCM2_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_MSM_REQ0,

	}, {

		.peri_id = (u8)DMACH_MSM_REQ2,

	}, {

		.peri_id = (u8)DMACH_SPI0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SPI0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SPI2_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SPI2_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_I2S0S_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_I2S0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_I2S0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_UART0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_UART0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_UART2_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_UART2_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_UART4_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_UART4_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS2_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS2_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS4_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS4_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_AC97_MICIN,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_AC97_PCMIN,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_AC97_PCMOUT,

		.rqtype = MEMTODEV,

	},

u8 pdma0_peri[] = {

	DMACH_PCM0_RX,

	DMACH_PCM0_TX,

	DMACH_PCM2_RX,

	DMACH_PCM2_TX,

	DMACH_MSM_REQ0,

	DMACH_MSM_REQ2,

	DMACH_SPI0_RX,

	DMACH_SPI0_TX,

	DMACH_SPI2_RX,

	DMACH_SPI2_TX,

	DMACH_I2S0S_TX,

	DMACH_I2S0_RX,

	DMACH_I2S0_TX,

	DMACH_I2S2_RX,

	DMACH_I2S2_TX,

	DMACH_UART0_RX,

	DMACH_UART0_TX,

	DMACH_UART2_RX,

	DMACH_UART2_TX,

	DMACH_UART4_RX,

	DMACH_UART4_TX,

	DMACH_SLIMBUS0_RX,

	DMACH_SLIMBUS0_TX,

	DMACH_SLIMBUS2_RX,

	DMACH_SLIMBUS2_TX,

	DMACH_SLIMBUS4_RX,

	DMACH_SLIMBUS4_TX,

	DMACH_AC97_MICIN,

	DMACH_AC97_PCMIN,

	DMACH_AC97_PCMOUT,

};



struct dma_pl330_platdata exynos4_pdma0_pdata = {

	.nr_valid_peri = ARRAY_SIZE(pdma0_peri),

	.peri = pdma0_peri,

	.peri_id = pdma0_peri,

};



struct amba_device exynos4_device_pdma0 = {
@@ -142,86 +89,37 @@ struct amba_device exynos4_device_pdma0 = { 
	.periphid = 0x00041330,

};



struct dma_pl330_peri pdma1_peri[25] = {

	{

		.peri_id = (u8)DMACH_PCM0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_PCM0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_PCM1_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_PCM1_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_MSM_REQ1,

	}, {

		.peri_id = (u8)DMACH_MSM_REQ3,

	}, {

		.peri_id = (u8)DMACH_SPI1_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SPI1_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_I2S0S_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_I2S0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_I2S0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_I2S1_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_I2S1_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_UART0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_UART0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_UART1_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_UART1_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_UART3_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_UART3_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS1_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS1_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS3_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS3_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS5_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS5_TX,

		.rqtype = MEMTODEV,

	},

u8 pdma1_peri[] = {

	DMACH_PCM0_RX,

	DMACH_PCM0_TX,

	DMACH_PCM1_RX,

	DMACH_PCM1_TX,

	DMACH_MSM_REQ1,

	DMACH_MSM_REQ3,

	DMACH_SPI1_RX,

	DMACH_SPI1_TX,

	DMACH_I2S0S_TX,

	DMACH_I2S0_RX,

	DMACH_I2S0_TX,

	DMACH_I2S1_RX,

	DMACH_I2S1_TX,

	DMACH_UART0_RX,

	DMACH_UART0_TX,

	DMACH_UART1_RX,

	DMACH_UART1_TX,

	DMACH_UART3_RX,

	DMACH_UART3_TX,

	DMACH_SLIMBUS1_RX,

	DMACH_SLIMBUS1_TX,

	DMACH_SLIMBUS3_RX,

	DMACH_SLIMBUS3_TX,

	DMACH_SLIMBUS5_RX,

	DMACH_SLIMBUS5_TX,

};



struct dma_pl330_platdata exynos4_pdma1_pdata = {

	.nr_valid_peri = ARRAY_SIZE(pdma1_peri),

	.peri = pdma1_peri,

	.peri_id = pdma1_peri,

};



struct amba_device exynos4_device_pdma1 = {
@@ -242,7 +140,12 @@ struct amba_device exynos4_device_pdma1 = { 


static int __init exynos4_dma_init(void)

{

	dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);

	dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);

	amba_device_register(&exynos4_device_pdma0, &iomem_resource);



	dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);

	dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);

	amba_device_register(&exynos4_device_pdma1, &iomem_resource);



	return 0;