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Commit e1bd1c63 authored by Xiaoyu Ye's avatar Xiaoyu Ye
Browse files

ARM: dts: msm: add QUAT TDM pinctrl configurations on SDM845 



Add pinctrl nodes for QUAT TDM to provide pinctrl settings
on SDM845.

Change-Id: I04c502c177f59c60cd6e98b3e39d982331b3207f
Signed-off-by: default avatarXiaoyu Ye <benyxy@codeaurora.org>
parent 5f300da0

arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi

+84 −0
Original line number Diff line number Diff line
@@ -1400,6 +1400,90 @@ 
			};

		};



		quat_tdm {

			quat_tdm_sleep: quat_tdm_sleep {

				mux {

					pins = "gpio58", "gpio59";

					function = "qua_mi2s";

				};



				config {

					pins = "gpio58", "gpio59";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

				};

			};



			quat_tdm_active: quat_tdm_active {

				mux {

					pins = "gpio58", "gpio59";

					function = "qua_mi2s";

				};



				config {

					pins = "gpio58", "gpio59";

					drive-strength = <8>;   /* 8 mA */

					bias-disable;           /* NO PULL */

				};

			};

		};



		quat_tdm_dout {

			quat_tdm_dout_sleep: quat_tdm_dout_sleep {

				mux {

					pins = "gpio61";

					function = "qua_mi2s";

				};



				config {

					pins = "gpio61";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

				};

			};



			quat_tdm_dout_active: quat_tdm_dout_active {

				mux {

					pins = "gpio61";

					function = "qua_mi2s";

				};



				config {

					pins = "gpio61";

					drive-strength = <2>;   /* 2 mA */

					bias-disable;           /* NO PULL */

				};

			};

		};



		quat_tdm_din {

			quat_tdm_din_sleep: quat_tdm_din_sleep {

				mux {

					pins = "gpio60";

					function = "qua_mi2s";

				};



				config {

					pins = "gpio60";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

				};

			};



			quat_tdm_din_active: quat_tdm_din_active {

				mux {

					pins = "gpio60";

					function = "qua_mi2s";

				};



				config {

					pins = "gpio60";

					drive-strength = <2>;   /* 2 mA */

					bias-disable;           /* NO PULL */

				};

			};

		};



		/* QUPv3 South SE mappings */

		/* SE 0 pin mappings */

		qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {