igb: add pf side of VMDq support

#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */

#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000

#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000

#define E1000_SRRCTL_DROP_EN                            0x80000000

#define E1000_MRQC_ENABLE_RSS_4Q            0x00000002

#define E1000_MRQC_ENABLE_VMDQ              0x00000003

#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q       0x00000005

#define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000

#define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000

#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000

#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */

#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */

/* Easy defines for setting default pool, would normally be left a zero */

#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7

#define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)

/* Other useful VMD_CTL register defines */

#define E1000_VT_CTL_IGNORE_MAC         (1 << 28)

#define E1000_VT_CTL_DISABLE_DEF_POOL   (1 << 29)

#define E1000_VT_CTL_VM_REPL_EN         (1 << 30)

/* Per VM Offload register setup */

#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */

#define E1000_VMOLR_LPE        0x00010000 /* Accept Long packet */

#define E1000_VMOLR_RSSE       0x00020000 /* Enable RSS */

#define E1000_VMOLR_AUPE       0x01000000 /* Accept untagged packets */

#define E1000_VMOLR_ROMPE      0x02000000 /* Accept overflow multicast */

#define E1000_VMOLR_ROPE       0x04000000 /* Accept overflow unicast */

#define E1000_VMOLR_BAM        0x08000000 /* Accept Broadcast packets */

#define E1000_VMOLR_MPME       0x10000000 /* Multicast promiscuous mode */

#define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */

#define ALL_QUEUES   0xFFFF

#endif

#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */

#define E1000_RAL_MAC_ADDR_LEN 4

#define E1000_RAH_MAC_ADDR_LEN 2

#define E1000_RAH_POOL_MASK 0x03FC0000

#define E1000_RAH_POOL_1 0x00040000

/* Error Codes */

#define E1000_ERR_NVM      1

#define E1000_RAH(_i)  (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \

                                       (0x054E4 + ((_i - 16) * 8)))

#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */

#define E1000_VMD_CTL  0x0581C  /* VMDq Control - RW */

#define E1000_VT_CTL   0x0581C  /* VMDq Control - RW */

#define E1000_WUC      0x05800  /* Wakeup Control - RW */

#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */

#define E1000_WUS      0x05810  /* Wakeup Status - RO */

#define E1000_RETA(_i)  (0x05C00 + ((_i) * 4))

#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */

/* VT Registers */

#define E1000_QDE       0x02408 /* Queue Drop Enable - RW */

/* These act per VF so an array friendly macro is used */

#define E1000_VMOLR(_n)        (0x05AD0 + (4 * (_n)))

#define wr32(reg, value) (writel(value, hw->hw_addr + reg))

#define rd32(reg) (readl(hw->hw_addr + reg))

#define wrfl() ((void)rd32(E1000_STATUS))

#define IGB_RXBUFFER_2048  2048

#define IGB_RXBUFFER_16384 16384

/* Packet Buffer allocations */

#define MAX_STD_JUMBO_FRAME_SIZE 9234

/* How many Tx Descriptors do we need to call netif_wake_queue ? */

#define IGB_TX_QUEUE_WAKE	16

	regs_buff[34] = rd32(E1000_RLPML);

	regs_buff[35] = rd32(E1000_RFCTL);

	regs_buff[36] = rd32(E1000_MRQC);

	regs_buff[37] = rd32(E1000_VMD_CTL);

	regs_buff[37] = rd32(E1000_VT_CTL);

	/* Transmit */

	regs_buff[38] = rd32(E1000_TCTL);