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Commit e0b047bd authored by Murali Karicheri's avatar Murali Karicheri Committed by Mark Brown
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spi: davinci: change the lower limit of pre-scale divider to 1 



SPI hardware spec for Keystone specify a lower value of 0 for pre-scale
divider which determine what max value of spi clock (spi-max-frequency)
the device can support. This translates to a clock divider of 2. So fix
the lower limit value used for the boundary check in
davinci_spi_get_prescale() function to 1 so that a maximum of spi device
clock rate / 2 is possible to be set for spi-max-frequency.

Signed-off-by: default avatarMurali Karicheri <m-karicheri2@ti.com>
Acked-by: default avatarSekhar Nori <nsekhar@ti.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent b787f68c

drivers/spi/spi-davinci.c

+1 −1
Original line number Diff line number Diff line
@@ -265,7 +265,7 @@ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, 


	ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);



	if (ret < 3 || ret > 256)

	if (ret < 1 || ret > 256)

		return -EINVAL;



	return ret - 1;