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Commit e023d014 authored by Tony Truong's avatar Tony Truong Committed by Gerrit - the friendly Code Review server
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msm: pcie: fix PCIe L0s and L1 ASPM support 



Correct PCIe capability base address when checking
child L0s and L1 capability.

Change-Id: I7c5e5c8d4b1fdbc62e4e4b47f9ad15305f17a5cc
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent be27e35c

drivers/pci/host/pci-msm.c

+3 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -5560,7 +5560,7 @@ static void msm_pcie_config_link_pm_rc(struct msm_pcie_dev_t *dev, 
			u32 val;



			pci_read_config_dword(child_pdev,

				pdev->pcie_cap + PCI_EXP_LNKCTL, &val);

				child_pdev->pcie_cap + PCI_EXP_LNKCTL, &val);

			child_l0s_enable = !!(val & PCI_EXP_LNKCTL_ASPM_L0S);

			if (child_l0s_enable)

				break;
@@ -5608,7 +5608,7 @@ static void msm_pcie_config_link_pm_rc(struct msm_pcie_dev_t *dev, 
			u32 val;



			pci_read_config_dword(child_pdev,

				pdev->pcie_cap + PCI_EXP_LNKCTL, &val);

				child_pdev->pcie_cap + PCI_EXP_LNKCTL, &val);

			child_l1_enable = !!(val & PCI_EXP_LNKCTL_ASPM_L1);

			if (child_l1_enable)

				break;