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Commit e00c8d74 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Move global memory region to 0x100000000"

parents 76750afe 756d6a94

drivers/gpu/msm/adreno.c

+2 −2
Original line number Diff line number Diff line
@@ -1517,7 +1517,7 @@ static void _set_secvid(struct kgsl_device *device) 
		adreno_writereg64(adreno_dev,

			ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

			ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,

			KGSL_IOMMU_SECURE_BASE);

			KGSL_IOMMU_SECURE_BASE(&device->mmu));

		adreno_writereg(adreno_dev,

			ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE,

			KGSL_IOMMU_SECURE_SIZE);
@@ -2101,7 +2101,7 @@ static int adreno_getproperty(struct kgsl_device *device, 
				 * anything to mmap().

				 */

				shadowprop.gpuaddr =

					(unsigned int) device->memstore.gpuaddr;

					(unsigned long)device->memstore.gpuaddr;

				shadowprop.size = device->memstore.size;

				/* GSL needs this to be set, even if it

				 * appears to be meaningless

drivers/gpu/msm/adreno_a5xx.c

+2 −2
Original line number Diff line number Diff line
@@ -2424,8 +2424,8 @@ static int a5xx_rb_start(struct adreno_device *adreno_dev, 
	adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_CNTL,

		A5XX_CP_RB_CNTL_DEFAULT);



	adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_BASE,

			rb->buffer_desc.gpuaddr);

	adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_BASE,

			ADRENO_REG_CP_RB_BASE_HI, rb->buffer_desc.gpuaddr);



	ret = a5xx_microcode_load(adreno_dev);

	if (ret)

drivers/gpu/msm/adreno_a6xx.c

+2 −2
Original line number Diff line number Diff line
@@ -1085,8 +1085,8 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev, 
	adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_CNTL,

					A6XX_CP_RB_CNTL_DEFAULT);



	adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_BASE,

			rb->buffer_desc.gpuaddr);

	adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_BASE,

			ADRENO_REG_CP_RB_BASE_HI, rb->buffer_desc.gpuaddr);



	ret = a6xx_microcode_load(adreno_dev);

	if (ret)

drivers/gpu/msm/kgsl_iommu.c

+23 −19
Original line number Diff line number Diff line
@@ -39,9 +39,10 @@ 


#define _IOMMU_PRIV(_mmu) (&((_mmu)->priv.iommu))



#define ADDR_IN_GLOBAL(_a) \

	(((_a) >= KGSL_IOMMU_GLOBAL_MEM_BASE) && \

	 ((_a) < (KGSL_IOMMU_GLOBAL_MEM_BASE + KGSL_IOMMU_GLOBAL_MEM_SIZE)))

#define ADDR_IN_GLOBAL(_mmu, _a) \

	(((_a) >= KGSL_IOMMU_GLOBAL_MEM_BASE(_mmu)) && \

	 ((_a) < (KGSL_IOMMU_GLOBAL_MEM_BASE(_mmu) + \

	 KGSL_IOMMU_GLOBAL_MEM_SIZE)))



/*

 * Flag to set SMMU memory attributes required to
@@ -185,7 +186,8 @@ int kgsl_iommu_map_global_secure_pt_entry(struct kgsl_device *device, 
	if (entry != NULL) {

		struct kgsl_pagetable *pagetable = device->mmu.securepagetable;

		entry->pagetable = pagetable;

		entry->gpuaddr = KGSL_IOMMU_SECURE_BASE + secure_global_size;

		entry->gpuaddr = KGSL_IOMMU_SECURE_BASE(&device->mmu) +

			secure_global_size;



		ret = kgsl_mmu_map(pagetable, entry);

		if (ret == 0)
@@ -224,7 +226,8 @@ static void kgsl_iommu_add_global(struct kgsl_mmu *mmu, 
			KGSL_IOMMU_GLOBAL_MEM_SIZE))

		return;



	memdesc->gpuaddr = KGSL_IOMMU_GLOBAL_MEM_BASE + global_pt_alloc;

	memdesc->gpuaddr = KGSL_IOMMU_GLOBAL_MEM_BASE(mmu) + global_pt_alloc;



	memdesc->priv |= KGSL_MEMDESC_GLOBAL;

	global_pt_alloc += memdesc->size;
@@ -642,7 +645,7 @@ static void _find_mem_entries(struct kgsl_mmu *mmu, uint64_t faultaddr, 
	/* Set the maximum possible size as an initial value */

	nextentry->gpuaddr = (uint64_t) -1;



	if (ADDR_IN_GLOBAL(faultaddr)) {

	if (ADDR_IN_GLOBAL(mmu, faultaddr)) {

		_get_global_entries(faultaddr, preventry, nextentry);

	} else if (context) {

		private = context->proc_priv;
@@ -1031,13 +1034,13 @@ static void setup_64bit_pagetable(struct kgsl_mmu *mmu, 
		struct kgsl_iommu_pt *pt)

{

	if (mmu->secured && pagetable->name == KGSL_MMU_SECURE_PT) {

		pt->compat_va_start = KGSL_IOMMU_SECURE_BASE;

		pt->compat_va_end = KGSL_IOMMU_SECURE_END;

		pt->va_start = KGSL_IOMMU_SECURE_BASE;

		pt->va_end = KGSL_IOMMU_SECURE_END;

		pt->compat_va_start = KGSL_IOMMU_SECURE_BASE(mmu);

		pt->compat_va_end = KGSL_IOMMU_SECURE_END(mmu);

		pt->va_start = KGSL_IOMMU_SECURE_BASE(mmu);

		pt->va_end = KGSL_IOMMU_SECURE_END(mmu);

	} else {

		pt->compat_va_start = KGSL_IOMMU_SVM_BASE32;

		pt->compat_va_end = KGSL_IOMMU_SVM_END32;

		pt->compat_va_end = KGSL_IOMMU_SECURE_BASE(mmu);

		pt->va_start = KGSL_IOMMU_VA_BASE64;

		pt->va_end = KGSL_IOMMU_VA_END64;

	}
@@ -1046,7 +1049,7 @@ static void setup_64bit_pagetable(struct kgsl_mmu *mmu, 
		pagetable->name != KGSL_MMU_SECURE_PT) {

		if ((BITS_PER_LONG == 32) || is_compat_task()) {

			pt->svm_start = KGSL_IOMMU_SVM_BASE32;

			pt->svm_end = KGSL_IOMMU_SVM_END32;

			pt->svm_end = KGSL_IOMMU_SECURE_BASE(mmu);

		} else {

			pt->svm_start = KGSL_IOMMU_SVM_BASE64;

			pt->svm_end = KGSL_IOMMU_SVM_END64;
@@ -1060,19 +1063,19 @@ static void setup_32bit_pagetable(struct kgsl_mmu *mmu, 
{

	if (mmu->secured) {

		if (pagetable->name == KGSL_MMU_SECURE_PT) {

			pt->compat_va_start = KGSL_IOMMU_SECURE_BASE;

			pt->compat_va_end = KGSL_IOMMU_SECURE_END;

			pt->va_start = KGSL_IOMMU_SECURE_BASE;

			pt->va_end = KGSL_IOMMU_SECURE_END;

			pt->compat_va_start = KGSL_IOMMU_SECURE_BASE(mmu);

			pt->compat_va_end = KGSL_IOMMU_SECURE_END(mmu);

			pt->va_start = KGSL_IOMMU_SECURE_BASE(mmu);

			pt->va_end = KGSL_IOMMU_SECURE_END(mmu);

		} else {

			pt->va_start = KGSL_IOMMU_SVM_BASE32;

			pt->va_end = KGSL_IOMMU_SECURE_BASE;

			pt->va_end = KGSL_IOMMU_SECURE_BASE(mmu);

			pt->compat_va_start = pt->va_start;

			pt->compat_va_end = pt->va_end;

		}

	} else {

		pt->va_start = KGSL_IOMMU_SVM_BASE32;

		pt->va_end = KGSL_IOMMU_GLOBAL_MEM_BASE;

		pt->va_end = KGSL_IOMMU_GLOBAL_MEM_BASE(mmu);

		pt->compat_va_start = pt->va_start;

		pt->compat_va_end = pt->va_end;

	}
@@ -2383,7 +2386,8 @@ static int kgsl_iommu_set_svm_region(struct kgsl_pagetable *pagetable, 
	struct rb_node *node;



	/* Make sure the requested address doesn't fall in the global range */

	if (ADDR_IN_GLOBAL(gpuaddr) || ADDR_IN_GLOBAL(gpuaddr + size))

	if (ADDR_IN_GLOBAL(pagetable->mmu, gpuaddr) ||

			ADDR_IN_GLOBAL(pagetable->mmu, gpuaddr + size))

		return -ENOMEM;



	spin_lock(&pagetable->lock);

drivers/gpu/msm/kgsl_iommu.h

+9 −4
Original line number Diff line number Diff line
@@ -24,12 +24,17 @@ 
 * are mapped into all pagetables.

 */

#define KGSL_IOMMU_GLOBAL_MEM_SIZE	(20 * SZ_1M)

#define KGSL_IOMMU_GLOBAL_MEM_BASE	0xf8000000

#define KGSL_IOMMU_GLOBAL_MEM_BASE32	0xf8000000

#define KGSL_IOMMU_GLOBAL_MEM_BASE64	TASK_SIZE_32



#define KGSL_IOMMU_GLOBAL_MEM_BASE(__mmu)	\

	(MMU_FEATURE(__mmu, KGSL_MMU_64BIT) ? \

		KGSL_IOMMU_GLOBAL_MEM_BASE64 : KGSL_IOMMU_GLOBAL_MEM_BASE32)



#define KGSL_IOMMU_SECURE_SIZE SZ_256M

#define KGSL_IOMMU_SECURE_END KGSL_IOMMU_GLOBAL_MEM_BASE

#define KGSL_IOMMU_SECURE_BASE	\

	(KGSL_IOMMU_GLOBAL_MEM_BASE - KGSL_IOMMU_SECURE_SIZE)

#define KGSL_IOMMU_SECURE_END(_mmu) KGSL_IOMMU_GLOBAL_MEM_BASE(_mmu)

#define KGSL_IOMMU_SECURE_BASE(_mmu)	\

	(KGSL_IOMMU_GLOBAL_MEM_BASE(_mmu) - KGSL_IOMMU_SECURE_SIZE)



#define KGSL_IOMMU_SVM_BASE32		0x300000

#define KGSL_IOMMU_SVM_END32		(0xC0000000 - SZ_16M)