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Commit dfcd8212 authored by Jan Glauber's avatar Jan Glauber Committed by Wolfram Sang
Browse files

i2c: octeon: Cleanup i2c-octeon driver 



Cleanup only without functional change.

- removed DRV_VERSION
- defines: use defines instead of plain values,
  use BIT_ULL macro, add comments
- rename waitqueue return value to time_left
- sort local variables by length
- fix indentation and whitespace errors
- make function return void if the result is not used
  (octeon_i2c_stop, octeon_i2c_set_clock)
- remove debug code from octeon_i2c_stop
- renamed some functions for readability
- update copyright

Signed-off-by: default avatarJan Glauber <jglauber@cavium.com>
Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
parent 7724fd04

drivers/i2c/busses/i2c-octeon.c

+84 −106
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
 * (C) Copyright 2009-2010

 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com

 *

 * Portions Copyright (C) 2010, 2011 Cavium Networks, Inc.

 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.

 *

 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.

 *
@@ -26,30 +26,34 @@ 


#define DRV_NAME "i2c-octeon"



/* The previous out-of-tree version was implicitly version 1.0. */

#define DRV_VERSION	"2.0"



/* register offsets */

/* Register offsets */

#define SW_TWSI			0x00

#define TWSI_INT		0x10



/* Controller command patterns */

#define SW_TWSI_V               0x8000000000000000ull

#define SW_TWSI_EOP_TWSI_DATA   0x0C00000100000000ull

#define SW_TWSI_EOP_TWSI_CTL    0x0C00000200000000ull

#define SW_TWSI_EOP_TWSI_CLKCTL 0x0C00000300000000ull

#define SW_TWSI_EOP_TWSI_STAT   0x0C00000300000000ull

#define SW_TWSI_EOP_TWSI_RST    0x0C00000700000000ull

#define SW_TWSI_OP_TWSI_CLK     0x0800000000000000ull

#define SW_TWSI_R               0x0100000000000000ull

#define SW_TWSI_V		BIT_ULL(63)	/* Valid bit */

#define SW_TWSI_R		BIT_ULL(56)	/* Result or read bit */



/* Controller opcode word (bits 60:57) */

#define SW_TWSI_OP_SHIFT	57

#define SW_TWSI_OP_TWSI_CLK	(4ULL << SW_TWSI_OP_SHIFT)

#define SW_TWSI_OP_EOP		(6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */



/* Controller extended opcode word (bits 34:32) */

#define SW_TWSI_EOP_SHIFT	32

#define SW_TWSI_EOP_TWSI_DATA	(SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)

#define SW_TWSI_EOP_TWSI_CTL	(SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)

#define SW_TWSI_EOP_TWSI_CLKCTL	(SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)

#define SW_TWSI_EOP_TWSI_STAT	(SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)

#define SW_TWSI_EOP_TWSI_RST	(SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)



/* Controller command and status bits */

#define TWSI_CTL_CE		0x80

#define TWSI_CTL_ENAB 0x40

#define TWSI_CTL_STA  0x20

#define TWSI_CTL_STP  0x10

#define TWSI_CTL_IFLG 0x08

#define TWSI_CTL_AAK  0x04

#define TWSI_CTL_ENAB		0x40	/* Bus enable */

#define TWSI_CTL_STA		0x20	/* Master-mode start, HW clears when done */

#define TWSI_CTL_STP		0x10	/* Master-mode stop, HW clears when done */

#define TWSI_CTL_IFLG		0x08	/* HW event, SW writes 0 to ACK */

#define TWSI_CTL_AAK		0x04	/* Assert ACK */



/* Some status values */

#define STAT_START		0x08
@@ -60,6 +64,11 @@ 
#define STAT_RXDATA_ACK		0x50

#define STAT_IDLE		0xF8



/* TWSI_INT values */

#define TWSI_INT_CORE_EN	BIT_ULL(6)

#define TWSI_INT_SDA_OVR	BIT_ULL(8)

#define TWSI_INT_SCL_OVR	BIT_ULL(9)



struct octeon_i2c {

	wait_queue_head_t queue;

	struct i2c_adapter adap;
@@ -80,9 +89,7 @@ struct octeon_i2c { 
 *

 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.

 */

static void octeon_i2c_write_sw(struct octeon_i2c *i2c,

				u64 eop_reg,

				u8 data)

static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data)

{

	u64 tmp;
@@ -93,7 +100,7 @@ static void octeon_i2c_write_sw(struct octeon_i2c *i2c, 
}



/**

 * octeon_i2c_read_sw - write an I2C core register

 * octeon_i2c_read_sw - read lower bits of an I2C core register

 * @i2c: The struct octeon_i2c

 * @eop_reg: Register selector

 *
@@ -133,12 +140,13 @@ static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) 
 */

static void octeon_i2c_int_enable(struct octeon_i2c *i2c)

{

	octeon_i2c_write_int(i2c, 0x40);

	octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);

}



/* disable the CORE interrupt */

static void octeon_i2c_int_disable(struct octeon_i2c *i2c)

{

	/* clear TS/ST/IFLG events */

	octeon_i2c_write_int(i2c, 0);

}
@@ -154,17 +162,19 @@ static void octeon_i2c_unblock(struct octeon_i2c *i2c) 
	int i;



	dev_dbg(i2c->dev, "%s\n", __func__);



	for (i = 0; i < 9; i++) {

		octeon_i2c_write_int(i2c, 0x0);

		octeon_i2c_write_int(i2c, 0);

		udelay(5);

		octeon_i2c_write_int(i2c, 0x200);

		octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);

		udelay(5);

	}

	octeon_i2c_write_int(i2c, 0x300);

	/* hand-crank a STOP */

	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);

	udelay(5);

	octeon_i2c_write_int(i2c, 0x100);

	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);

	udelay(5);

	octeon_i2c_write_int(i2c, 0x0);

	octeon_i2c_write_int(i2c, 0);

}



/* interrupt service routine */
@@ -192,17 +202,13 @@ static int octeon_i2c_test_iflg(struct octeon_i2c *i2c) 
 */

static int octeon_i2c_wait(struct octeon_i2c *i2c)

{

	long result;

	long time_left;



	octeon_i2c_int_enable(i2c);



	result = wait_event_timeout(i2c->queue,

					octeon_i2c_test_iflg(i2c),

	time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),

				       i2c->adap.timeout);



	octeon_i2c_int_disable(i2c);



	if (result == 0) {

	if (!time_left) {

		dev_dbg(i2c->dev, "%s: timeout\n", __func__);

		return -ETIMEDOUT;

	}
@@ -218,8 +224,8 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c) 
 */

static int octeon_i2c_start(struct octeon_i2c *i2c)

{

	u8 data;

	int result;

	u8 data;



	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,

			    TWSI_CTL_ENAB | TWSI_CTL_STA);
@@ -235,7 +241,6 @@ static int octeon_i2c_start(struct octeon_i2c *i2c) 
			octeon_i2c_unblock(i2c);

			octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,

					    TWSI_CTL_ENAB | TWSI_CTL_STA);



			result = octeon_i2c_wait(i2c);

		}

		if (result)
@@ -251,26 +256,11 @@ static int octeon_i2c_start(struct octeon_i2c *i2c) 
	return 0;

}



/**

 * octeon_i2c_stop - send STOP to the bus

 * @i2c: The struct octeon_i2c

 *

 * Returns 0 on success, otherwise a negative errno.

 */

static int octeon_i2c_stop(struct octeon_i2c *i2c)

/* send STOP to the bus */

static void octeon_i2c_stop(struct octeon_i2c *i2c)

{

	u8 data;



	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,

			    TWSI_CTL_ENAB | TWSI_CTL_STP);



	data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);



	if (data != STAT_IDLE) {

		dev_err(i2c->dev, "%s: bad status(0x%x)\n", __func__, data);

		return -EIO;

	}

	return 0;

}



/**
@@ -303,6 +293,7 @@ static int octeon_i2c_write(struct octeon_i2c *i2c, int target, 


	for (i = 0; i < length; i++) {

		tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);



		if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {

			dev_err(i2c->dev,

				"%s: bad status before write (0x%x)\n",
@@ -354,6 +345,7 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target, 


	for (i = 0; i < length; i++) {

		tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);



		if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {

			dev_err(i2c->dev,

				"%s: bad status before read (0x%x)\n",
@@ -385,17 +377,15 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target, 
 *

 * Returns the number of messages processed, or a negative errno on failure.

 */

static int octeon_i2c_xfer(struct i2c_adapter *adap,

			   struct i2c_msg *msgs,

static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,

			   int num)

{

	struct i2c_msg *pmsg;

	int i;

	int ret = 0;

	struct octeon_i2c *i2c = i2c_get_adapdata(adap);

	int i, ret = 0;



	for (i = 0; ret == 0 && i < num; i++) {

		pmsg = &msgs[i];

		struct i2c_msg *pmsg = &msgs[i];



		dev_dbg(i2c->dev,

			"Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",

			 pmsg->flags & I2C_M_RD ? "read" : "write",
@@ -430,7 +420,7 @@ static struct i2c_adapter octeon_i2c_ops = { 
};



/* calculate and set clock divisors */

static int octeon_i2c_setclock(struct octeon_i2c *i2c)

static void octeon_i2c_set_clock(struct octeon_i2c *i2c)

{

	int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;

	int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
@@ -438,8 +428,7 @@ static int octeon_i2c_setclock(struct octeon_i2c *i2c) 
	for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {

		/*

		 * An mdiv value of less than 2 seems to not work well

		 * with ds1337 RTCs, so we constrain it to larger

		 * values.

		 * with ds1337 RTCs, so we constrain it to larger values.

		 */

		for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {

			/*
@@ -449,6 +438,7 @@ static int octeon_i2c_setclock(struct octeon_i2c *i2c) 
			tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;

			tclk *= (1 << ndiv_idx);

			thp_base = (i2c->sys_freq / (tclk * 2)) - 1;



			for (inc = 0; inc <= 1; inc++) {

				thp_idx = thp_base + inc;

				if (thp_idx < 5 || thp_idx > 0xff)
@@ -469,11 +459,9 @@ static int octeon_i2c_setclock(struct octeon_i2c *i2c) 
	}

	octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);

	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);



	return 0;

}



static int octeon_i2c_initlowlevel(struct octeon_i2c *i2c)

static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)

{

	u8 status;

	int tries;
@@ -496,9 +484,10 @@ static int octeon_i2c_initlowlevel(struct octeon_i2c *i2c) 


static int octeon_i2c_probe(struct platform_device *pdev)

{

	int irq, result = 0;

	struct octeon_i2c *i2c;

	struct device_node *node = pdev->dev.of_node;

	struct resource *res_mem;

	struct octeon_i2c *i2c;

	int irq, result = 0;



	/* All adaptors have an irq.  */

	irq = platform_get_irq(pdev, 0);
@@ -507,7 +496,6 @@ static int octeon_i2c_probe(struct platform_device *pdev) 


	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);

	if (!i2c) {

		dev_err(&pdev->dev, "kzalloc failed\n");

		result = -ENOMEM;

		goto out;

	}
@@ -528,10 +516,8 @@ static int octeon_i2c_probe(struct platform_device *pdev) 
	 * "clock-frequency".  Try the official one first and then

	 * fall back if it doesn't exist.

	 */

	if (of_property_read_u32(pdev->dev.of_node,

				 "clock-frequency", &i2c->twsi_freq) &&

	    of_property_read_u32(pdev->dev.of_node,

				 "clock-rate", &i2c->twsi_freq)) {

	if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&

	    of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {

		dev_err(i2c->dev,

			"no I2C 'clock-rate' or 'clock-frequency' property\n");

		result = -ENXIO;
@@ -558,21 +544,17 @@ static int octeon_i2c_probe(struct platform_device *pdev) 
		goto out;

	}



	result = octeon_i2c_initlowlevel(i2c);

	result = octeon_i2c_init_lowlevel(i2c);

	if (result) {

		dev_err(i2c->dev, "init low level failed\n");

		goto  out;

	}



	result = octeon_i2c_setclock(i2c);

	if (result) {

		dev_err(i2c->dev, "clock init failed\n");

		goto  out;

	}

	octeon_i2c_set_clock(i2c);



	i2c->adap = octeon_i2c_ops;

	i2c->adap.dev.parent = &pdev->dev;

	i2c->adap.dev.of_node = pdev->dev.of_node;

	i2c->adap.dev.of_node = node;

	i2c_set_adapdata(&i2c->adap, i2c);

	platform_set_drvdata(pdev, i2c);
@@ -581,8 +563,7 @@ static int octeon_i2c_probe(struct platform_device *pdev) 
		dev_err(i2c->dev, "failed to add adapter\n");

		goto out;

	}

	dev_info(i2c->dev, "version %s\n", DRV_VERSION);



	dev_info(i2c->dev, "probed\n");

	return 0;



out:
@@ -597,10 +578,8 @@ static int octeon_i2c_remove(struct platform_device *pdev) 
	return 0;

};



static struct of_device_id octeon_i2c_match[] = {

	{

		.compatible = "cavium,octeon-3860-twsi",

	},

static const struct of_device_id octeon_i2c_match[] = {

	{ .compatible = "cavium,octeon-3860-twsi", },

	{},

};

MODULE_DEVICE_TABLE(of, octeon_i2c_match);
@@ -619,4 +598,3 @@ module_platform_driver(octeon_i2c_driver); 
MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");

MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");

MODULE_LICENSE("GPL");
 
MODULE_VERSION(DRV_VERSION);